利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

57 条记录 (耗时 0.047 秒)

    EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION
    1.
    发明申请
    EFFICIENCY OF STATIC CORE TURN-OFF IN A SYSTEM-ON-A-CHIP WITH VARIATION 失效
    静态芯片在带有变化的系统中的关闭效率

    公开(公告)号：US20110172984A1

    公开(公告)日：2011-07-14

    申请号：US12727984

    申请日：2010-03-19

    申请人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    发明人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    IPC分类号： G06F9/455

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/3237 ,  G06F11/24 ,  Y02D10/128 ,  Y02D10/16

    摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

    摘要翻译： 一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析 其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出 核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

    Efficiency of static core turn-off in a system-on-a-chip with variation
    3.
    发明授权
    Efficiency of static core turn-off in a system-on-a-chip with variation 失效
    在具有变化的片上系统中静态磁芯关断的效率

    公开(公告)号：US08571847B2

    公开(公告)日：2013-10-29

    申请号：US12727984

    申请日：2010-03-19

    申请人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    发明人： Chen-Yong Cher ,  Paul W. Coteus ,  Alan Gara ,  Eren Kursun ,  David P. Paulsen ,  Brian A. Schuelke ,  John E. Sheets, II ,  Shurong Tian

    IPC分类号： G06G7/75

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  G06F1/3237 ,  G06F11/24 ,  Y02D10/128 ,  Y02D10/16

    摘要： A processor-implemented method for improving efficiency of a static core turn-off in a multi-core processor with variation, the method comprising: conducting via a simulation a turn-off analysis of the multi-core processor at the multi-core processor's design stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's design stage includes a first output corresponding to a first multi-core processor core to turn off; conducting a turn-off analysis of the multi-core processor at the multi-core processor's testing stage, wherein the turn-off analysis of the multi-core processor at the multi-core processor's testing stage includes a second output corresponding to a second multi-core processor core to turn off; comparing the first output and the second output to determine if the first output is referring to the same core to turn off as the second output; outputting a third output corresponding to the first multi-core processor core if the first output and the second output are both referring to the same core to turn off.

    摘要翻译： 一种用于提高多核处理器中的静态核心关断的效率的处理器实现的方法，所述方法包括：通过模拟在多核处理器的设计处进行多核处理器的关断分析 其中所述多核处理器的设计阶段的所述多核处理器的关断分析包括对应于第一多核处理器核的第一输出关闭; 在多核处理器的测试阶段对多核处理器进行关断分析，其中多核处理器的测试阶段的多核处理器的关断分析包括对应于第二多核处理器的第二多输出 核心处理器核心关闭; 比较第一输出和第二输出以确定第一输出是否指相同的磁芯作为第二输出关闭; 如果第一输出和第二输出均指向相同的核来关闭，则输出对应于第一多核处理器核心的第三输出。

    Implementing eFuse circuit with enhanced eFuse blow operation
    5.
    发明授权
    Implementing eFuse circuit with enhanced eFuse blow operation 失效
    实现eFuse电路，增强eFuse吹扫操作

    公开(公告)号：US08492207B2

    公开(公告)日：2013-07-23

    申请号：US13091259

    申请日：2011-04-21

    申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

    发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

    IPC分类号： H01L21/762

    CPC分类号： H01L23/5256 ,  H01H2085/0283 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and an eFuse circuit for implementing with enhanced eFuse blow operation without requiring a separate high current and high voltage supply to blow the eFuse, and a design structure on which the subject circuit resides are provided. The eFuse circuit includes an eFuse connected to a field effect transistor (FET) operatively controlled during a sense mode and a blow mode for sensing and blowing the eFuse. The eFuse circuit is placed over an independently voltage controlled silicon region. During a sense mode, the independently voltage controlled silicon region is grounded providing an increased threshold voltage of the FET. During a blow mode, the independently voltage controlled silicon region is charged to a voltage supply potential. The threshold voltage of the FET is reduced by the charged independently voltage controlled silicon region for providing enhanced FET blow function.

    摘要翻译： 一种用于在不需要单独的高电流和高电压来吹送eFuse的情况下实现增强的eFuse吹扫操作的方法和eFuse电路，并且提供了主题电路所在的设计结构。 eFuse电路包括连接到在感测模式期间可操作地控制的场效应晶体管（FET）的eFuse和用于感测和吹送eFuse的吹扫模式。 eFuse电路放置在独立的电压控制的硅​​区域上。 在感测模式期间，独立的受电压控制的硅​​区域被接地，从而提供FET增加的阈值电压。 在吹扫模式期间，独立的受控硅区域被充电到电压供应电位。 通过充电的独立电压控制的硅​​区域来降低FET的阈值电压，以提供增强的FET吹扫功能。

    INDEPENDENTLY VOLTAGE CONTROLLED VOLUME OF SILICON ON A SILICON ON INSULATOR CHIP
    7.
    发明申请
    INDEPENDENTLY VOLTAGE CONTROLLED VOLUME OF SILICON ON A SILICON ON INSULATOR CHIP 有权
    绝缘子芯片上硅的独立电压控制体积

    公开(公告)号：US20120267752A1

    公开(公告)日：2012-10-25

    申请号：US13091275

    申请日：2011-04-21

    申请人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

    发明人： Karl R. Erickson ,  Phil C. Paone ,  David P. Paulsen ,  John E. Sheets, II ,  Gregory J. Uhlmann ,  Kelly L. Williams

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L21/2652 ,  H01L21/76267 ,  H01L29/1087

    摘要： A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

    摘要翻译： 半导体芯片具有独立的电压控制硅区域，其是用于控制eDRAM沟槽电容器的电容值和覆盖独立电压控制的硅​​区域的场效应晶体管的阈值电压的电路元件。 独立电压控制的硅​​区域的底部或底部是与独立电压控制的硅​​区域的衬底的掺杂相反掺杂的深度注入。 独立电压控制的硅​​区域的顶部或天花板是衬底中的埋入氧化物植入物。 独立电压控制的硅​​区域的侧面是深沟槽隔离。 独立电压控制的硅​​区域的电压通过埋入氧化物形成的接触结构施加。

    Bias Temperature Instability-Influenced Storage Cell
    9.
    发明申请
    Bias Temperature Instability-Influenced Storage Cell 失效
    偏压温度不稳定影响存储单元

    公开(公告)号：US20110013445A1

    公开(公告)日：2011-01-20

    申请号：US12505102

    申请日：2009-07-17

    申请人： Douglas M. Dewanz ,  Peter T. Freiburger ,  David P. Paulsen ,  John E. Sheets, II

    发明人： Douglas M. Dewanz ,  Peter T. Freiburger ,  David P. Paulsen ,  John E. Sheets, II

    IPC分类号： G11C11/00 ,  G11C8/08 ,  G11C7/04

    CPC分类号： G11C16/04 ,  G11C2013/008

    摘要： In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line is driven to a high voltage state. The word line is driven to a predetermined voltage state that causes bias temperature instability in the FET. The temperature, the high voltage state on the bit line and the predetermined voltage state on the word line are maintained for an amount of time sufficient to change a threshold voltage of the FET to a state where a desired data value is stored on the FET. The FET is cooled to a second temperature that is cooler than the first temperature after the amount of time has expired.

    摘要翻译： 在使用采用场效应晶体管（FET）的存储单元的方法中，将FET加热到足以支持FET中的偏置温度不稳定性的第一温度。 位线被驱动到高电压状态。 字线被驱动到导致FET中的偏置温度不稳定性的预定电压状态。 将位线上的温度，位线上的高电压状态和字线上的预定电压状态保持足以将FET的阈值电压改变到期望数据值存储在FET上的状态的时间量。 在时间到期后，将FET冷却至比第一温度更冷的第二温度。