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1.发明授权Method, apparatus and computer program product for implementing enhanced notification and control features in oscilloscopes 失效用于在示波器中实现增强型通知和控制功能的方法，设备和计算机程序产品公开(公告)号：US06917900B2
公开(公告)日：2005-07-12
申请号：US10660031
申请日：2003-09-11
CPC分类号： G01R13/029 , G01R13/20
摘要： A method, apparatus and computer program product are provided for implementing enhanced notification and control features in an oscilloscope. User selected notification options and user selected control options are stored. When a predefined event is identified, the user selected notification options are used for notifying a remote user of the identified predefined event. The user selected control options are used for receiving user selections enabling the user to remotely control oscilloscope operational settings. The user can be notified with a telephone call, an email or a pager text message and the user can change operational settings using a telephone call or an email containing commands.
摘要翻译： 提供了一种用于在示波器中实现增强的通知和控制特征的方法，装置和计算机程序产品。 用户选择的通知选项和用户选择的控制选项被存储。 当识别出预定义的事件时，用户选择的通知选项用于向远程用户通知所识别的预定事件。 用户选择的控制选项用于接收用户选择，使用户能够远程控制示波器的操作设置。 可以通过电话呼叫，电子邮件或寻呼机短信通知用户，并且用户可以使用电话呼叫或包含命令的电子邮件来改变操作设置。
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2.发明申请METHOD AND APPARATUS FOR IMPLEMENTING BALANCED CLOCK DISTRIBUTION NETWORKS ON ASICS WITH VOLTAGE ISLANDS FUNCTIONING AT MULTIPLE OPERATING POINTS OF VOLTAGE AND TEMPERATURE 有权用于在电压和温度的多个操作点上实现具有电压岛功能的ASICS上的平衡时钟分配网络的方法和装置公开(公告)号：US20090179680A1
公开(公告)日：2009-07-16
申请号：US12014172
申请日：2008-01-15
CPC分类号： H03K5/1502 , G06F1/10
摘要： A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.
摘要翻译： 一种在具有在电压和温度的多个工作点处工作的电压岛的专用集成电路（ASIC）上实现平衡时钟分配网络的方法和装置，以及提供主题电路所在的设计结构。 时钟源耦合到提供时钟信号的N电平平衡时钟树。 多个电压岛中的每一个包括相应的电压移位器和接收时钟信号的可编程延迟功能。 每个相应的电压移位器和可编程延迟功能为相关电压岛的相应的平衡时钟树提供第二时钟信号。 系统控制器为每个相应的电压移位器和可编程延迟功能提供相应的控制输入。 相应的控制输入根据各个电压岛的操作模式动态变化。
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3.发明授权Implementing logic security feature for disabling integrated circuit test ports ability to scanout data 有权实现逻辑安全功能，禁用集成电路测试端口扫描数据的能力公开(公告)号：US08166357B2
公开(公告)日：2012-04-24
申请号：US11964093
申请日：2007-12-26
IPC分类号： G01R31/28
CPC分类号： G01R31/31719
摘要： A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.
摘要翻译： 提供一种用于实现集成电路安全特征的方法和装置，以选择性地禁用集成电路芯片上的可测试性特征。 测试禁止逻辑电路接收测试使能信号并响应于测试模式的测试使能信号设置，建立测试模式并禁用ASIC信号。 响应于未设置的测试使能信号，ASIC信号使能功能模式，并且集成电路芯片上的可测试功能被禁用。 当启用功能模式时，测试禁止逻辑电路可防止在集成电路芯片通电时建立测试模式。
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4.发明申请Method and Apparatus for Implementing Logic Security Feature for Disabling Integrated Circuit Test Ports Ability to Scanout Data 有权实现逻辑安全特性的方法和装置，用于禁用集成电路测试端口能够扫描数据公开(公告)号：US20090172819A1
公开(公告)日：2009-07-02
申请号：US11964093
申请日：2007-12-26
IPC分类号： G06F21/22
CPC分类号： G01R31/31719
摘要： A method and apparatus for implementing integrated circuit security features are provided to selectively disable testability features on an integrated circuit chip. A test disable logic circuit receives a test enable signal and responsive to the test enable signal set for a test mode, establishes a test mode and disables ASIC signals. Responsive to the test enable signal not being set, the ASIC signals are enabled for a functional mode and the testability features on the integrated circuit chip are disabled. When the functional mode is enabled, the test disable logic circuit prevents the test mode from being established while the integrated circuit chip is powered up.
摘要翻译： 提供一种用于实现集成电路安全特征的方法和装置，以选择性地禁用集成电路芯片上的可测试性特征。 测试禁止逻辑电路接收测试使能信号并响应于测试模式的测试使能信号设置，建立测试模式并禁用ASIC信号。 响应于未设置的测试使能信号，ASIC信号使能功能模式，并且集成电路芯片上的可测试功能被禁用。 当启用功能模式时，测试禁止逻辑电路可防止在集成电路芯片通电时建立测试模式。
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公开(公告)号：US6011412A
公开(公告)日：2000-01-04
申请号：US70925
申请日：1998-05-01
IPC分类号： H03D13/00
CPC分类号： H03D13/004
摘要： A frequency shift detection circuit for detecting a frequency shift between a first signal and a second signal includes two or more delay circuits coupled to one another in series and two or more comparison logic circuits. The first delay circuit in the series receives one of the first and second signals and produces a delayed replica. Each of the other delay circuits receives the delayed replica produced by the previous delay circuit in the series and produces a further delayed replica. Thus, the signal produced by each delay circuit is delayed from the original signal by a different amount. Each comparison logic circuit receives one of the delayed replicas and receives the other one of the first and second signals, i.e., the one that is not received by the delay circuits. In response, the comparison logic circuit produces a frequency shift detection signal when it detects a phase difference between that other one of said first and second signals and the delayed replica. By selecting or tapping one of the outputs of the comparison logic circuits, a user can select the detection granularity.
摘要翻译： 用于检测第一信号和第二信号之间的频移的频移检测电路包括串联耦合的两个或更多个延迟电路和两个或更多个比较逻辑电路。 该系列中的第一个延迟电路接收第一和第二信号中的一个并产生延迟的副本。 每个其他延迟电路接收由串联中的先前延迟电路产生的延迟复制品，并产生另一延迟复制品。 因此，由每个延迟电路产生的信号从原始信号延迟不同的量。 每个比较逻辑电路接收一个延迟的副本并且接收第一和第二信号中的另一个，即未被延迟电路接收的信号。 作为响应，当比较逻辑电路检测到所述第一和第二信号中的另一个与延迟的副本之间的相位差时，产生频移检测信号。 通过选择或敲击比较逻辑电路的输出之一，用户可以选择检测粒度。
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公开(公告)号：US5977837A
公开(公告)日：1999-11-02
申请号：US071447
申请日：1998-05-01
CPC分类号： G06F1/10 , H03L7/06 , H03L7/095 , Y10S331/02
摘要： A method for removing an external frequency divider and clock formation circuit from a feedback path of a phase locked loop and a phase selector circuit are provided for synchronizing an external frequency divider with a reference clock of a phase locked loop. A reference clock signal is applied to the phase locked loop. An output of the phase locked loop is coupled through a predefined delay and provides a delayed feedback clock signal input to the phase locked loop. The external frequency divider is located at the output of the phase locked loop external to the predefined delay and outside the feedback clock signal path of the phase locked loop. A phase selector circuit identifies a correct phase of the reference clock signal and starts the external frequency divider. The phase selector circuit includes an edge detector, a synchronization divider, and a reset machine.
摘要翻译： 提供了一种从锁相环和相位选择器电路的反馈路径去除外部分频器和时钟形成电路的方法，用于使外部分频器与锁相环的参考时钟同步。 参考时钟信号被施加到锁相环。 锁相环的输出通过预定义的延迟耦合，并提供延迟的反馈时钟信号输入到锁相环。 外部分频器位于预定义延迟外部的锁相环的输出端，并位于锁相环的反馈时钟信号路径之外。 相位选择器电路识别参考时钟信号的正确相位并启动外部分频器。 相位选择器电路包括边缘检测器，同步分配器和复位机。
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7.发明授权Method and apparatus for implementing balanced clock distribution networks on ASICs with voltage islands functioning at multiple operating points of voltage and temperature 有权用于在电压岛在电压和温度的多个工作点处工作的ASIC上实现平衡时钟分配网络的方法和装置公开(公告)号：US07551002B1
公开(公告)日：2009-06-23
申请号：US12014172
申请日：2008-01-15
IPC分类号： H03K19/00
CPC分类号： H03K5/1502 , G06F1/10
摘要： A method and apparatus implement balanced clock distribution networks on application specific integrated circuits (ASICs) with voltage islands functioning at multiple operating points of voltage and temperature, and a design structure on which the subject circuit resides is provided. A clock source is coupled to an N-level balanced clock tree providing a clock signal. Each of a plurality of voltage islands includes a respective voltage shifter and programmable delay function receiving the clock signal. Each respective voltage shifter and programmable delay function provides a second clock signal to a respective balanced clock tree for the associated voltage island. A system controller provides a respective control input to each respective voltage shifter and programmable delay function. The respective control input is varied dynamically corresponding to an operational mode of the respective voltage island.
摘要翻译： 一种在具有在电压和温度的多个工作点处工作的电压岛的专用集成电路（ASIC）上实现平衡时钟分配网络的方法和装置，以及提供主题电路所在的设计结构。 时钟源耦合到提供时钟信号的N电平平衡时钟树。 多个电压岛中的每一个包括相应的电压移位器和接收时钟信号的可编程延迟功能。 每个相应的电压移位器和可编程延迟功能为相关电压岛的相应的平衡时钟树提供第二时钟信号。 系统控制器为每个相应的电压移位器和可编程延迟功能提供相应的控制输入。 相应的控制输入根据各个电压岛的操作模式动态变化。
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公开(公告)号：US5764712A
公开(公告)日：1998-06-09
申请号：US634504
申请日：1996-04-18
CPC分类号： H03L7/10 , H03L7/113 , Y10S331/02
摘要： A method for setting a locking frequency operating range of the phase locked loop (PLL) circuit and a phase locked loop (PLL) circuit are provided with range select logic for detecting an unknown reference clock frequency and for setting a locking frequency operating range of the phase locked loop. First a bypass mode for the phase locked loop (PLL) circuit is set. An unknown reference clock frequency is applied to a first counter. A known oscillator clock frequency is applied to a second counter. The first and second counters are reset and a timeout value of the second counter is identified. A first counter count value is compared with precalculated constant values. A set of range bits are latched responsive to said compared values. Two consecutive sets of latched range bits are compared and the steps repeated until a match of two consecutive sets of latched range bits is identified. The matching latched range bits are applied to a programmable range select input of the phase locked loop (PLL) circuit.
摘要翻译： 用于设置锁相环（PLL）电路和锁相环（PLL）电路的锁定频率工作范围的方法设置有用于检测未知参考时钟频率的范围选择逻辑，并且用于设置锁相环 锁相环。 首先设置锁相环（PLL）电路的旁路模式。 将未知的参考时钟频率应用于第一个计数器。 已知的振荡器时钟频率被施加到第二计数器。 第一和第二计数器被复位，并且识别出第二计数器的超时值。 将第一计数器计数值与预先计算的常数值进行比较。 响应于所述比较值而锁存一组范围位。 比较两个连续的锁存范围比特组，并重复步骤，直到两个连续的锁存范围比特组的匹配被识别。 匹配的锁存范围位被应用于锁相环（PLL）电路的可编程范围选择输入。
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