公开(公告)号：US20170287458A1

公开(公告)日：2017-10-05

申请号：US15626147

申请日：2017-06-18

申请人： Brian James Kaczynski ,  Noam Lavi

发明人： Brian James Kaczynski ,  Noam Lavi

IPC分类号： G10H5/00 ,  H03M7/16 ,  H03L7/16

CPC分类号： G10H5/002 ,  G06F1/022 ,  G10H2250/101 ,  G10H2250/161 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/0992 ,  H03L7/16 ,  H03L7/181 ,  H03L7/197 ,  H03L2207/50 ,  H03M7/16

摘要： Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again. This FLL circuit is also preceded by a low-pass filter which is dynamically tuned to the frequency to which the FLL locks, eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation.

公开(公告)号：US20130335250A1

公开(公告)日：2013-12-19

申请号：US13527291

申请日：2012-06-19

申请人： Sotirios LIMOTYRAKIS ,  Michael Peter MACK ,  Hyunsik PARK ,  Sang-Min LEE ,  Brian James KACZYNSKI ,  MeeLan LEE

发明人： Sotirios LIMOTYRAKIS ,  Michael Peter MACK ,  Hyunsik PARK ,  Sang-Min LEE ,  Brian James KACZYNSKI ,  MeeLan LEE

IPC分类号： H03M1/38

CPC分类号： H03M1/46 ,  H03M1/1225 ,  H03M1/145 ,  H03M1/164 ,  H03M1/361

摘要： A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.

摘要翻译： 可以实现混合SAR ADC，以减少将模拟输入信号转换为其数字表示所执行的操作次数。 可以在模拟输入信号上执行流水线处理操作以产生流水线位（数字表示的MSB）和模拟残差信号。 可以将模拟残留信号与多个阈值进行比较，以产生指示与对应于模拟残留信号的预定阈值的子集相关联的范围的比较器位。 可以对模拟残差信号执行连续近似模数转换操作，以生成逐次逼近位。 可以至少部分地基于流水线比特，比较器比特和逐次逼近比特来确定数字表示。

公开(公告)号：US09824673B2

公开(公告)日：2017-11-21

申请号：US15626147

申请日：2017-06-18

申请人： Brian James Kaczynski ,  Noam Lavi

发明人： Brian James Kaczynski ,  Noam Lavi

IPC分类号： G10H5/00 ,  G10H1/06 ,  H03L7/16 ,  H03M7/16

CPC分类号： G10H5/002 ,  G06F1/022 ,  G10H2250/101 ,  G10H2250/161 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/0992 ,  H03L7/16 ,  H03L7/181 ,  H03L7/197 ,  H03L2207/50 ,  H03M7/16

摘要： Methods and digital circuits providing frequency correction to frequency synthesizers are disclosed. An FLL digital circuit is provided that is configured to handle a reference frequency that is dynamic and ranges over a multi-decade range of frequencies. The FLL circuit includes a digital frequency iteration engine that allows for detection of disappearance of a reference frequency. When the digital frequency iteration engine detects that the reference frequency signal is not available, the oscillator generated frequency is not corrected, and the last value of the oscillator generated frequency is held until the reference frequency signal becomes available again. This FLL circuit is also preceded by a low-pass filter which is dynamically tuned to the frequency to which the FLL locks, eliminating harmonic components in the original signal which might otherwise cause errors in frequency estimation.

公开(公告)号：US08614638B1

公开(公告)日：2013-12-24

申请号：US13527291

申请日：2012-06-19

申请人： Sotirios Limotyrakis ,  Michael Peter Mack ,  Hyunsik Park ,  Sang-Min Lee ,  Brian James Kaczynski ,  MeeLan Lee

发明人： Sotirios Limotyrakis ,  Michael Peter Mack ,  Hyunsik Park ,  Sang-Min Lee ,  Brian James Kaczynski ,  MeeLan Lee

IPC分类号： H03M1/38

CPC分类号： H03M1/46 ,  H03M1/1225 ,  H03M1/145 ,  H03M1/164 ,  H03M1/361

摘要： A hybrid SAR ADC can be implemented to reduce the number of operations that are executed to convert an analog input signal into its digital representation. Pipeline processing operations can be executed on the analog input signal to generate pipeline bits (MSBs of the digital representation) and an analog residue signal. The analog residue signal can be compared against a plurality of thresholds to generate comparator bits that are indicative of a range associated with a subset of the predetermined thresholds that correspond to the analog residue signal. Successive approximation analog-to-digital conversion operations can be executed on the analog residue signal to generate successive approximation bits. The digital representation can be determined based, at least in part, on the pipeline bits, the comparator bits, and the successive approximation bits.

摘要翻译： 可以实现混合SAR ADC，以减少将模拟输入信号转换为其数字表示所执行的操作次数。 可以在模拟输入信号上执行流水线处理操作以产生流水线位（数字表示的MSB）和模拟残差信号。 可以将模拟残留信号与多个阈值进行比较，以产生指示与对应于模拟残留信号的预定阈值的子集相关联的范围的比较器位。 可以对模拟残差信号执行连续近似模数转换操作，以生成逐次逼近位。 可以至少部分地基于流水线比特，比较器比特和逐次逼近比特来确定数字表示。