公开(公告)号：US5931957A

公开(公告)日：1999-08-03

申请号：US829669

申请日：1997-03-31

申请人： Brian R Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

发明人： Brian R Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F11/00 ,  G06F9/30

CPC分类号： G06F9/30043 ,  G06F9/3834 ,  G06F9/3861

摘要： To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.

摘要翻译： 为了支持关于存储指令执行无序的加载指令，实现了一种机制来检测（和校正）在逻辑上先前的存储指令之前执行的加载指令的发生，并且其中加载指令接收数据为 由存储指令修改之前的位置，以及加载指令的正确数据，包括来自存储指令的字节。 另外，为了执行与加载指令无序的存储指令，实现了一种机制来保持存储指令不会破坏由逻辑上较早的加载指令使用的数据。 此外，为了支持相对于彼此执行的无序执行的加载指令，实现一种机制以确保任何一对加载指令（其访问至少一个共同的字节）返回数据与执行加载指令一致 为了。

公开(公告)号：US6021467A

公开(公告)日：2000-02-01

申请号：US713056

申请日：1996-09-12

申请人： Brian R. Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

发明人： Brian R. Konigsburg ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F12/0859 ,  G06F12/0897 ,  Y02B60/1225

摘要： An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request. The present invention reduces the number of accesses to the level two cache and allows data requests to be satisfied in parallel versus serially when multiple successive level one cache misses occur.

摘要翻译： 一种用于处理信息处理系统中的多个高速缓存未命中到单个高速缓存行的装置和方法，该信息处理系统包括用于存储不在一级高速缓存中的数据的请求的未命中队列，以及比较器，用于将存储在所述未命中队列中的数据的请求与 确定是否存在针对二级缓存的同一高速缓存行中的数据的多个请求。 来自与二级缓存相同的高速缓存行的数据的新请求作为旧队列中的数据的较早原始请求被标记为加载命中重新加载。 标记为加载命中重载的请求随后与匹配的原始请求分组在一起并一起转发到二级缓存，其中原始请求请求来自二级缓存的数据。 加载命中重新加载请求不访问二级缓存，而是通过从匹配的原始请求的二级缓存输出的高速缓存行中提取数据来绕过二级缓存的访问。 本发明减少对二级高速缓存的访问次数，并且允许当发生多个连续一级高速缓存未命中时并行地对数据请求进行满足。

公开(公告)号：US5802571A

公开(公告)日：1998-09-01

申请号：US734318

申请日：1996-10-21

申请人： Brian R. Konigsburg ,  John Stephen Muhich ,  Steven Wayne White

发明人： Brian R. Konigsburg ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F12/12 ,  G06F12/08

CPC分类号： G06F12/0859

摘要： An age-based arbitration scheme for enforcing data coherency in an information handling system is disclosed. As loads and stores access a cache, if a cache miss occurs, a miss request is generated and tagged with the cycle or age in which the miss is detected. If a castout is required, it is also tagged with the cycle in which the load or store access occurred, and the line being replaced or cast out is marked as being invalid in that level of hierarchy. The arbitration rules for the next level of memory hierarchy are defined such that all requests that are generated during a particular cycle are given priority over all of the requests generated during any subsequent cycle. As a result, if a load miss occurs for a cache line which is present in the castout buffer, the castout request tagged with an earlier age will be arbitrated into the next memory hierarchy level prior to the arrival of the newly generated miss requests. The age-based arbitration scheme can also be used for multiple cache accesses occurring in parallel.

摘要翻译： 公开了一种用于在信息处理系统中执行数据一致性的基于年龄的仲裁方案。 当加载和存储访问缓存时，如果发生高速缓存未命中，则会生成错误请求并标记检测到未命中的周期或年龄。 如果需要castout，它也会被标记为发生加载或存储访问的循环，并且被替换或丢弃的行在该级别的级别中被标记为无效。 定义下一级存储器层级的仲裁规则，使得在特定周期期间生成的所有请求优先于在任何后续周期期间生成的所有请求。 结果，如果对于存在于转储缓冲器中的高速缓存行发生负载缺失，则在新生成的未命中请求到达之前，具有较早年龄的标记的转换请求将被仲裁到下一个存储器层级中。 基于年龄的仲裁方案也可以用于并行发生的多个高速缓存访​​问。

公开(公告)号：US06412051B1

公开(公告)日：2002-06-25

申请号：US08757979

申请日：1996-11-27

申请人： Brian R. Konigsburg ,  George McNeil Lattimore ,  John Stephen Muhich

发明人： Brian R. Konigsburg ,  George McNeil Lattimore ,  John Stephen Muhich

IPC分类号： G06F1214

CPC分类号： G11C29/88 ,  G06F12/126 ,  G06F2212/1032 ,  G11C15/00 ,  G11C2029/0409

摘要： A system and method for allowing operation of a storage array after a failure within a set of an n-way set associative cache includes determining that there is a failure in a bit line in the storage array, setting a flag to inhibit access to the portion of the array accessed by the failing entity and storing and retrieving data from remaining portions of the array. The present invention is well adapted for use with n-way set associative cache storage arrays.

摘要翻译： 一种用于允许在一组n路组相关高速缓存中的故障之后存储阵列的操作的系统和方法包括确定存储阵列中位线中存在故障，设置禁止访问该部分的标志 由数据库的剩余部分存储和检索数据。 本发明适用于与n路组相关高速缓存存储阵列的使用。

公开(公告)号：US5870582A

公开(公告)日：1999-02-09

申请号：US829671

申请日：1997-03-31

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38

CPC分类号： G06F9/3855 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3863

摘要： In a method and apparatus for allocating processor resources in a data processing system, instructions are dispatched and tagged for processing. A processor resource snoops to obtain execution results for the tagged instructions. Such an instruction is logically "finished" in response to determining that it will not cause an interrupt (which includes not changing the sequence of completing instructions), and "completed" in response to finishing all earlier dispatched instructions. Information is entered for such an instructions in rename buffer in response to the instruction targeting an architected register, and such a rename buffer entry is released in response to completing the entry's instruction. The rename buffer may comprise a history buffer. Also, information for the instructions is entered in a completion queue in response to dispatching the instructions, and the queue entry for such an instruction is released in response to completion of the instruction. Also, the instructions are grouped, a group having solely a single interruptible instruction, and further including non-interruptible instructions dispatched following the interruptible instruction. Thus, there may be numerous non-interruptible instructions in such a group. Such an interruptible instruction is logically "finished" in response to determining that it will not cause an interrupt, and "completed" in response to finishing all earlier dispatched instructions. Such a non-interruptible instruction is logically "finished" and "completed" in response to completion of its associated interruptible instruction, so that such a non-interruptible instruction may complete before it is dispatched.

摘要翻译： 在用于在数据处理系统中分配处理器资源的方法和装置中，调度和标记用于处理的指令。 处理器资源被窥探以获得标记指令的执行结果。 响应于确定不会导致中断（其不包括改变完成指令的顺序），并且响应于完成所有先前分派的指令而“完成”，这样的指令在逻辑上“完成”。 响应于针对架构化寄存器的指令，在重命名缓冲器中输入这样的指令的信息，并且响应于完成条目的指令而释放这样的重命名缓冲器条目。 重命名缓冲器可以包括历史缓冲器。 此外，响应于分派指令，将指令的信息输入到完成队列中，并且响应于指令的完成而释放这样的指令的队列条目。 此外，指令被分组，仅具有单个可中断指令的组，并且还包括在可中断指令之后分派的不可中断指令。 因此，在这样的组中可能存在许多不可中断的指令。 这种可中断指令在逻辑上“完成”以响应于确定它不会引起中断，并且响应于完成所有先前分派的指令而“完成”。 响应于其相关联的可中断指令的完成，这种不可中断指令被逻辑地“完成”和“完成”，使得这种不可中断指令可以在其被分派之前完成。

公开(公告)号：US5864341A

公开(公告)日：1999-01-26

申请号：US761875

申请日：1996-12-06

申请人： Troy Neal Hicks ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Troy Neal Hicks ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3891 ,  G06F9/3824 ,  G06F9/3853 ,  G06F9/3885

摘要： The present invention is directed to a method and apparatus for dispatching instructions in an information handling system. A pre-execution queue stores instructions, and at least one execution cluster is operably coupled to the pre-execution queue. An execution cluster comprises an early execution unit for executing a first instruction dispatched from the pre-execution queue to generate and forward a first result and a late execution unit for executing a second instruction dispatched from the pre-execution queue to generate and forward a second result after the first execution unit forwards the first result. The invention further includes circuitry operably associated with the pre-execution queue, and a method for prioritizing the order in which the instructions in the pre-execution queue are dispatched to the execution cluster.

摘要翻译： 本发明涉及一种用于在信息处理系统中调度指令的方法和装置。 预执行队列存储指令，并且至少一个执行群集可操作地耦合到预执行队列。 执行群包括一个早期执行单元，用于执行从预执行队列发出的第一指令，以产生和转发第一结果;以及后期执行单元，用于执行从预执行队列发出的第二指令，以产生和转发第二个 第一执行单元转发第一个结果后的结果。 本发明还包括可操作地与预执行队列相关联的电路，以及用于将预执行队列中的指令分派到执行群集的顺序的优先级的方法。

公开(公告)号：US5860014A

公开(公告)日：1999-01-12

申请号：US729307

申请日：1996-10-15

申请人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

发明人： Hoichi Cheong ,  Hung Qui Le ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3861

摘要： A method and apparatus for maintaining content of registers of a processor which uses the registers for processing instructions. Entries are stored in a buffer for restoring register content in response to an interruption by an interruptible instruction. Entries include information for reducing the number of entries selected for the restoring. A set of the buffer entries is selected, in response to the interruption and the information, for restoring register content. The set includes only entries which are necessary for restoring the content in response to the interruption so that the content of the processor registers may be restored in a single processor cycle, even if multiple entries are stored for a first one of the registers and multiple entries are stored for a second one of the registers.

摘要翻译： 一种用于维护使用寄存器处理指令的处理器的寄存器的内容的方法和装置。 条目存储在缓冲器中，用于通过可中断指令中断来恢复寄存器内容。 条目包括用于减少为恢复选择的条目数量的信息。 响应于中断和信息来选择一组缓冲器条目用于恢复寄存器内容。 该集合仅包括为了响应于中断而恢复内容所必需的条目，使得处理器寄存器的内容可以在单个处理器周期中被恢复，即使对于第一个寄存器和多个条目存储了多个条目 存储在第二个寄存器中。

公开(公告)号：US5784604A

公开(公告)日：1998-07-21

申请号：US959183

申请日：1992-10-09

申请人： John Stephen Muhich ,  Terrence Matthew Potter ,  Steven Wayne White

发明人： John Stephen Muhich ,  Terrence Matthew Potter ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3804

摘要： A method and system are disclosed for reducing run-time delay during conditional branch instruction execution in a pipelined processor system. A series of queued sequential instructions and conditional branch instructions are processed wherein each conditional branch instruction specifies an associated conditional branch to be taken in response to a selected outcome of processing one or more sequential instructions. Upon detection of a conditional branch instruction within the queue, a group of target instructions are fetched based upon a prediction that an associated conditional branch will be taken. Sequential instructions within the queue following the conditional branch instruction are then purged and the target instructions loaded into the queue only in response to a successful a retrieval of the target instructions, such that the sequential instructions may be processed without delay if the prediction that the conditional branch is taken proves invalid prior to retrieval of the target instructions. Alternately, the purged sequential instructions may be refetched after loading the target instructions such that the sequential instructions may be executed with minimal delay if the prediction that the conditional branch is taken proves invalid after loading the target instructions. In yet another embodiment, the sequential instructions within the queue following the conditional branch instruction are purged only in response to a successful retrieval of the target instructions and an imminent execution of the conditional branch instruction.

摘要翻译： 公开了一种用于在流水线处理器系统中的条件分支指令执行期间减少运行时间延迟的方法和系统。 处理一系列排队的顺序指令和条件分支指令，其中每个条件分支指令响应于处理一个或多个顺序指令的所选结果来指定要采取的相关联的条件分支。 在检测到队列内的条件分支指令之后，基于将采用相关联的条件分支的预测来取得一组目标指令。 随后条件分支指令之后的队列中的顺序指令被清除，并且目标指令仅仅响应于目标指令的成功检索而被加载到队列中，使得如果预测条件 在检索目标指令之前，分支被认为是无效的。 或者，可以在加载目标指令之后重新抽取清除的顺序指令，使得如果在加载目标指令之后条件分支的预测被证明是无效的，则可以以最小延迟执行顺序指令。 在另一个实施例中，仅在响应于目标指令的成功检索和条件分支指令的即将执行之后才清除在条件分支指令之后的队列内的顺序指令。

公开(公告)号：US6167500A

公开(公告)日：2000-12-26

申请号：US131789

申请日：1998-08-10

申请人： Kurt Alan Feiste ,  John Stephen Muhich ,  Steven Wayne White

发明人： Kurt Alan Feiste ,  John Stephen Muhich ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F12/00

CPC分类号： G06F9/3867 ,  G06F9/3824

摘要： A mechanism and method for a store data queue are implemented. Address translation operations for store instructions in a data processor are decoupled from data operations by initiating address translation before source data operands are available. A store data queue snoops the finish buses of execution units for the source operand. A data entry in the data queue that is allocated at dispatch of the store instruction snoops for the source operand required by its corresponding instruction. The data operand is then communicated to a memory device in instruction order thereby simplifying the detection of conflicting stores.

摘要翻译： 实现了存储数据队列的机制和方法。 数据处理器内存储指令的地址转换操作通过在源数据操作数可用之前发起地址转换与数据操作分离。 存储数据队列窥探源操作数的执行单元的完成总线。 数据队列中的数据条目，在其对应指令所要求的源操作数的分派中分配存储指令侦听。 然后以指令顺序将数据操作数传送到存储器件，从而简化了冲突存储的检测。

公开(公告)号：US6021485A

公开(公告)日：2000-02-01

申请号：US826854

申请日：1997-04-10

申请人： Kurt Alan Feiste ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

发明人： Kurt Alan Feiste ,  John Stephen Muhich ,  Larry Edward Thatcher ,  Steven Wayne White

IPC分类号： G06F9/38 ,  G06F12/00 ,  G06F9/34

CPC分类号： G06F9/3816 ,  G06F9/30079 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3863

摘要： In a superscalar processor implementing out-of-order dispatching and execution of load and store instructions, when a store instruction has already been translated, the load address range of a load instruction is contained within the address range of the store instruction, and the data associated with the store instruction is available, then the data associated with the store instruction is forwarded to the load instruction so that the load instruction may continue execution without having to be stalled or flushed.

摘要翻译： 在执行无序调度和执行加载和存储指令的超标量处理器中，当存储指令已经被翻译时，加载指令的加载地址范围包含在存储指令的地址范围内，并且数据 与存储指令相关联的可用，则与存储指令相关联的数据被转发到加载指令，使得加载指令可以继续执行而不必被停止或刷新。