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    HASH MAP SUPPORT IN A STORAGE DEVICE
    2.
    发明申请
    HASH MAP SUPPORT IN A STORAGE DEVICE 有权
    存储设备中的HASH地图支持

    公开(公告)号：US20150278208A1

    公开(公告)日：2015-10-01

    申请号：US14228822

    申请日：2014-03-28

    申请人： Annie Foong ,  Bryan E. Veal

    发明人： Annie Foong ,  Bryan E. Veal

    IPC分类号： G06F17/30

    CPC分类号： G06F3/0659 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688

    摘要： In an embodiment, a storage device may include device processing logic. The device processing logic may acquire a command associated with a key-value pair (KVP). The command may be, for example, a get, set, or delete command. The KVP may include a hash value and an item. The hash value may be a key in the KVP and the item may be a value in the KVP. The device processing logic may translate the acquired command into one or more block-oriented commands which may be executed by the device processing logic to perform various operations on the storage device.

    摘要翻译： 在一个实施例中，存储设备可以包括设备处理逻辑。 设备处理逻辑可以获取与键值对（KVP）相关联的命令。 该命令可以是例如get，set或delete命令。 KVP可以包括散列值和项目。 散列值可以是KVP中的密钥，并且该项可以是KVP中的值。 设备处理逻辑可以将所获取的命令转换成一个或多个面向块的命令，该命令可由设备处理逻辑执行以在存储设备上执行各种操作。

    METHOD AND APPARATUS FOR SYNCHRONIZING STORAGE VOLUMES
    3.
    发明申请
    METHOD AND APPARATUS FOR SYNCHRONIZING STORAGE VOLUMES 有权
    用于同步存储体积的方法和装置

    公开(公告)号：US20140089728A1

    公开(公告)日：2014-03-27

    申请号：US13628257

    申请日：2012-09-27

    申请人： Bryan E. Veal ,  Annie Foong

    发明人： Bryan E. Veal ,  Annie Foong

    IPC分类号： G06F11/20

    CPC分类号： G06F11/1474

    摘要： A disk array redundancy controller ensures integrity of a mirrored or RAID storage array supporting a host system and minimizes recovery time responsive to a storage volume failure by traversing caches of recently written blocks to identify partially flushed stripes of data and recovering the inconsistent stripes on each of the storage volumes based on a master copy derived from the scan of all pre-failure caches of the storage array. The storage array employs nonvolatile caches in conjunction with solid state drive (SSD) storage volumes, allowing post-failure recovery of recently written blocks. A cache depth at least sufficient to store the largest stripe, or set of blocks, from the host ensures recovery of the entire stripe from a collective scan of the caches of all storage volumes of the storage array.

    摘要翻译： 磁盘阵列冗余控制器确保支持主机系统的镜像或RAID存储阵列的完整性，并通过遍历最近写入的块的高速缓存来最小化响应于存储卷故障的恢复时间，以识别部分刷新的数据条带，并恢复每个 存储卷基于从扫描存储阵列的所有故障前高速缓存得到的主副本。 存储阵列采用与固态驱动器（SSD）存储卷结合的非易失性高速缓存，允许最近写入的块的故障后恢复。 至少足以存储来自主机的最大条带或一组块的高速缓存深度确保从存储阵列的所有存储卷的高速缓存的集合扫描中恢复整个条带。

    COMMUNICATION BETWEEN PROCESSOR CORE PARTITIONS
    5.
    发明申请
    COMMUNICATION BETWEEN PROCESSOR CORE PARTITIONS 失效
    处理器核心部分之间的通信

    公开(公告)号：US20090319705A1

    公开(公告)日：2009-12-24

    申请号：US12141725

    申请日：2008-06-18

    申请人： Annie Foong ,  Bryan E. Veal ,  Arun Raghunath

    发明人： Annie Foong ,  Bryan E. Veal ,  Arun Raghunath

    IPC分类号： G06F13/00

    CPC分类号： G06F15/16

    摘要： In an embodiment, a method is provided that may include providing a first address space exclusively and coherently accessible by a first processor core partition in a platform. A second address space may be provided in this embodiment that is exclusively and coherently accessible by a second processor core partition in the platform. Also in this embodiment, a third address space in the platform may be provided that is accessible, at least in part, by both the first and second processor core partitions and may be to permit communication between the first and second processor core partitions of at least one packet and at least one descriptor associated with the at least one packet. The at least one descriptor may indicate, at least in part, one or more locations in the third address space to store, at least in part, the at least one packet. Of course, many alternatives, modifications, and variations are possible without departing from this embodiment.

    摘要翻译： 在一个实施例中，提供了一种方法，其可以包括提供由平台中的第一处理器核心分区独占且可相干访问的第一地址空间。 可以在该实施例中提供第二地址空间，其由平台中的第二处理器核心分区专门地和相干地访问。 同样在该实施例中，可以提供平台中的第三地址空间，其至少部分地由第一和第二处理器核分区可访问，并且可以允许至少在第一和第二处理器核分区之间进行通信 一个分组和与所述至少一个分组相关联的至少一个描述符。 至少一个描述符可以至少部分地指示第三地址空间中的一个或多个位置，以至少部分地存储至少一个分组。 当然，在不脱离本实施例的情况下，许多替代，修改和变化是可能的。

    ADAPTIVE RECEIVE SIDE SCALING
    6.
    发明申请
    ADAPTIVE RECEIVE SIDE SCALING 审中-公开
    适应性接收面尺寸

    公开(公告)号：US20090006521A1

    公开(公告)日：2009-01-01

    申请号：US11771250

    申请日：2007-06-29

    申请人： Bryan E. Veal ,  Annie Foong

    发明人： Bryan E. Veal ,  Annie Foong

    IPC分类号： G06F15/16

    CPC分类号： H04L45/00 ,  H04L45/38 ,  H04L45/745 ,  H04L47/125

    摘要： Receive side scaling in a network system may be improved by moving the task of adapting the load distribution from the operating system (“OS”) to the network device. A load feedback mechanism may be used for the OS to report per-core load to the network device. With per-core load information from the OS as well as its own knowledge of new flows, the network device is able to map new flows to the least-utilized cores by changing these cores' entries in an indirection table in the network device directly.

    摘要翻译： 可以通过将将操作系统（“OS”）的负载分配调整到网络设备的任务来改进网络系统中的接收侧缩放。 OS可以使用负载反馈机制来向网络设备报告每个核心的负载。 通过使用来自OS的每个核心负载信息以及它自己对新流的知识，网络设备能够通过直接在网络设备的间接表中改变这些核心的条目来将新的流映射到最不利用的核心。

    Method and device to augment volatile memory in a graphics subsystem with non-volatile memory
    7.
    发明授权
    Method and device to augment volatile memory in a graphics subsystem with non-volatile memory 有权
    在具有非易失性存储器的图形子系统中增加易失性存储器的方法和装置

    公开(公告)号：US09317892B2

    公开(公告)日：2016-04-19

    申请号：US13977261

    申请日：2011-12-28

    申请人： Bryan E. Veal ,  Travis T. Schluessler ,  Murali Ramadoss ,  Balaji Vembu

    发明人： Bryan E. Veal ,  Travis T. Schluessler ,  Murali Ramadoss ,  Balaji Vembu

    IPC分类号： G09G5/39 ,  G06T1/60 ,  G11C16/34

    CPC分类号： G06T1/60 ,  G11C16/349

    摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

    摘要翻译： 描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。 在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。 该方法还包括执行图形应用的图形处理器。 图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。 该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

    Source Core Interrupt Steering
    9.
    发明申请
    Source Core Interrupt Steering 有权
    源核心中断转向

    公开(公告)号：US20110153893A1

    公开(公告)日：2011-06-23

    申请号：US12641604

    申请日：2009-12-18

    申请人： Annie Foong ,  Bryan E. Veal

    发明人： Annie Foong ,  Bryan E. Veal

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24 ,  G06F9/4812

    摘要： An embodiment of the invention includes (i) receiving a core identifier that corresponds with a processor source core; (ii) receiving an input/output request, produced from the source core, that is associated with the core identifier; (iii) and directing an interrupt, which corresponds to the request, to the source core based on the core identifier. Other embodiments are described herein.

    摘要翻译： 本发明的实施例包括（i）接收与处理器源核心对应的核心标识符; （ii）从所述源核心接收与所述核心标识符相关联的输入/输出请求; （iii）并且基于核心标识符将对应于请求的中断引导到源核心。 本文描述了其它实施例。