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公开(公告)号：US20250068779A1
公开(公告)日：2025-02-27
申请号：US18454307
申请日：2023-08-23
Inventor： Arun R. Ramani , Amar Vellanki , Brent W. Wilson , Nathan D. P. Buchanan
Abstract: An integrated circuit (IC), including multiple registers and functional units for performing operations of the integrated circuit, provides security of register accesses. A bus interface controller coupled to the registers provides read/write access from bus interface. The IC includes a state controller for managing multiple operational modes, and an access control manager coupled to the state controller and the bus interface controller that asserts a dynamic lock over the accesses to the registers according to a selected operating mode and one or more protected addresses of the addressable register space corresponding to the current operating mode. A data screener compares data associated with the read or write accesses to sets of valid or invalid data values for the current operating mode and the protected addresses, and the access control manager permits or denies the read or write accesses in conformity with a result of the comparison.
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2.发明申请公开(公告)号：US20250062674A1
公开(公告)日：2025-02-20
申请号：US18450552
申请日：2023-08-16
Inventor： Shashank ALEVOOR , Siddharth MARU , Pietro GALLINA , Chanchal GUPTA , Vivek PARASURAM
Abstract: A method may include, when in a low-power mode of a power converter, monitoring an output voltage of the power converter; comparing, with a single comparator, the output voltage to a first threshold voltage and cause the power converter to enter a magnetization phase of the low-power mode responsive to the output voltage falling below the first threshold voltage; and during the magnetization phase and a demagnetization phase of the low-power mode, comparing, with the single comparator, the output voltage to a second threshold voltage lower than the first threshold voltage and cause the power converter to enter the high-power mode responsive to the output voltage falling below the second threshold voltage.
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公开(公告)号：US20250047293A1
公开(公告)日：2025-02-06
申请号：US18921418
申请日：2024-10-21
Inventor： Gavin MCVEIGH
Abstract: The present disclosure relates to a compensation circuit for compensating for an offset voltage that is present in an output signal output by a force sensor. The compensation circuit comprises: voltage divider circuitry, the voltage divider circuitry configured to receive a bias voltage that is also supplied to the force sensor and to output a control voltage derived from the bias voltage, wherein a component mismatch ratio of the voltage divider circuitry is adjustable to correspond to a component mismatch ratio of the force sensor; current generator circuitry configured to receive the control voltage and to generate a compensating current based on the received control voltage; and amplifier circuitry configured to receive the differential signal output by the force sensor and the compensating current and to output a compensated differential output signal in which the offset voltage is at least partially cancelled.
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公开(公告)号：US20250030387A1
公开(公告)日：2025-01-23
申请号：US18224770
申请日：2023-07-21
Inventor： John P. LESSO , Douglas J.W. MACFARLANE , John L. MELANSON
Abstract: This application relates to methods and apparatus for switching drivers. The switching driver has first and second switches for selectively connecting an output node to first and second switching voltages respectively to generate a first output voltage. A compensator is configured to receive a first monitor signal indicative of a sum of the first and second switching voltages and a second monitor signal indicative of a difference between the first and second switching voltages and to apply compensation to the input signal based on the first and second monitor signals so as to compensate for variations in the first and second switching voltages from defined nominal values of the first and second switching voltages. A modulator controls a duty cycle of the first and second switches based on the input signal after said compensation has been applied.
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公开(公告)号：US12191766B2
公开(公告)日：2025-01-07
申请号：US18505849
申请日：2023-11-09
Inventor： Changjong Lim
Abstract: A power converter for converting an input voltage at an input of the power converter into an output voltage at an output of the power converter may include a switching node, a power inductor coupled between the switching node and the output, a flying capacitor having a first flying capacitor terminal and a second flying capacitor terminal, a pump capacitor having a first pump capacitor terminal and a second pump capacitor terminal, the second pump capacitor terminal coupled to ground, a first switch coupled between the input and the first flying capacitor terminal, a second switch coupled between the first flying capacitor terminal and the switching node, a third switch coupled between the second flying capacitor terminal and the switching node, a fourth switch coupled between the second flying capacitor terminal and a ground voltage, a fifth switch coupled between the second flying capacitor terminal and the first pump capacitor terminal, and a sixth switch coupled between the output and the first pump capacitor terminal.
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Patent Agency Ranking
公开(公告)号：US12190716B2
公开(公告)日：2025-01-07
申请号：US18170277
申请日：2023-02-16
Inventor： Anthony S. Doy , Nermin Osmanovic , Carl L. Ståhl
Abstract: Embodiments described herein relate to methods and apparatus for outputting a haptic signal to a haptic transducer. A method for triggering a haptic signal being output to a haptic transducer comprises receiving an audio signal for output through an audio output transducer; determining whether the audio signal comprises a haptic trigger based on an indication of a rate of change of an amplitude of the audio signal, and responsive to determining that the audio signal comprises a haptic trigger, triggering the haptic signal to be output to the haptic transducer.
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公开(公告)号：US12184272B2
公开(公告)日：2024-12-31
申请号：US18308395
申请日：2023-04-27
Inventor： John P. Lesso , Douglas J. W. Macfarlane
IPC: H03K17/687 , H03K19/00 , H03K19/0185
Abstract: A switching transducer driver operable in: a first mode in which first and second output stage switches are controlled to generate a two-level output signal, wherein an impedance of the first output stage switch is substantially the same as an impedance of the second output stage switch; and a second mode in which the first and second output stage switches and a third switch are controlled to generate a three-level output signal, wherein an impedance of the third switch is substantially greater than the impedance of the first output stage switch and the second output stage switch.
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公开(公告)号：US20240429929A1
公开(公告)日：2024-12-26
申请号：US18824537
申请日：2024-09-04
Inventor： John L. MELANSON , Eric J. KING , Thomas H. HOFF , Lingli ZHANG
Abstract: Pulse width modulation (PWM) driver circuitry comprising: a loop filter configured to receive an analog input signal and to output a digital loop filter output signal based on the analog input signal and an analog feedback signal; and a PWM modulator configured to receive a digital signal based on the digital loop filter output signal and to output a PWM signal, wherein the PWM driver circuitry further comprises a feedback path coupled to an output of the PWM driver circuitry for the analog feedback signal.
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公开(公告)号：US12176781B2
公开(公告)日：2024-12-24
申请号：US16816833
申请日：2020-03-12
Inventor： Eric Lindemann , John L. Melanson , Emmanuel Marchais , Carl Lennart Ståhl
Abstract: A system for estimating parameters of an electromagnetic load may include an input for receiving an input excitation signal to the electromagnetic load, a broadband content estimator that identifies at least one portion of the input excitation signal having broadband content, and a parameter estimator that uses the at least one portion of the input excitation signal to estimate and output one or more parameters of the electromagnetic load.
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公开(公告)号：US12155299B2
公开(公告)日：2024-11-26
申请号：US18588723
申请日：2024-02-27
Inventor： Changjong Lim
Abstract: A power converter for converting an input voltage at an input of the power converter into an output voltage at an output of the power converter may include a first power converter branch comprising a first capacitor, a first switch network, and a first inductor, the first switch network arranged to selectably couple the first capacitor between an input voltage, a first reference voltage, and a first terminal of the first inductor, wherein a second terminal of the first inductor is coupled to an output node; a second power converter branch comprising a second capacitor, a second switch network, and a second inductor, the second switch network arranged to selectably couple the second capacitor between the input voltage, a second reference voltage, and a first terminal of the second inductor, wherein a second terminal of the second inductor is coupled to the output node; and a third switch network between the first power converter branch and the second power converter branch, wherein the third switch network is arranged to selectably couple the first and second capacitors in series or in parallel, to allow enable charge balancing between the first capacitor and second capacitor.
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