公开(公告)号：US20130111122A1

公开(公告)日：2013-05-02

申请号：US13285728

申请日：2011-10-31

申请人： Haoyu Song ,  Wang Xinyuan ,  Cao Wei

发明人： Haoyu Song ,  Wang Xinyuan ,  Cao Wei

IPC分类号： G06F12/00 ,  G06F12/06

CPC分类号： G06F13/1647 ,  G06F13/1684

摘要： An apparatus comprising a plurality of memory components each comprising a plurality of memory banks, a memory controller coupled to the memory components and configured to control and select a one of the plurality of memory components for a memory operation, a plurality of address/command buses coupled to the plurality of memory components and the memory controller comprising at least one shared address/command bus between at least some of the plurality of memory components, and a plurality of data buses coupled to the memory components and the memory controller comprising at least one data bus between at least some of the memory components, wherein the memory controller uses a memory interleaving and bank arbitration scheme in a time-division multiplexing (TDM) fashion to access the plurality of memory components and the memory banks.

摘要翻译： 一种装置，包括多个存储器组件，每个存储器组件包括多个存储器组，存储器控制器，耦合到存储器组件并被配置为控制和选择用于存储器操作的多个存储器组件中的一个，多个地址/命令总线 耦合到所述多个存储器组件，并且所述存储器控制器包括在所述多个存储器组件中的至少一些存储器组件之间的至少一个共享地址/命令总线以及耦合到所述存储器组件的多个数据总线以及包括至少一个 在至少一些存储器组件之间的数据总线，其中存储器控制器以时分复用（TDM）方式使用存储器交错和存储体仲裁方案来访问多个存储器组件和存储体。

公开(公告)号：US08519543B1

公开(公告)日：2013-08-27

申请号：US13551466

申请日：2012-07-17

申请人： Haoyu Song ,  Cao Wei ,  Rui Niu ,  Anwar A. Mohammed

发明人： Haoyu Song ,  Cao Wei ,  Rui Niu ,  Anwar A. Mohammed

IPC分类号： H01L23/48

CPC分类号： H01L23/147 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/17 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157

摘要： A multi-die integrated circuit assembly includes an interposer substrate larger than the typical reticle size used in fabricating the “active area” in which the through-silicon vias (TSVs) and interconnect conductors are formed in the interposer. At the same time, each of the dies has its external power/ground and I/O signal line connections concentrated into a smaller area of the die. The dies are disposed or mounted on the interposer such that these smaller areas (with the power/ground/IO connections) overlap with the active area of the interposer. In this configuration, a plurality of dies having a combined area substantially greater than the active area of the interposer can be mounted on the interposer (and take advantage of the active area for interconnections).

摘要翻译： 多模集成电路组件包括大于在制造其中在插入器中形成穿硅通孔（TSV）和互连导体的“有源区”中使用的典型标线尺寸的插入器基板。 同时，每个管芯都有其外部电源/接地和I / O信号线连接集中在芯片的较小区域。 模具设置或安装在插入器上，使得这些较小的区域（具有电源/接地/ IO连接）与插入器的有效区域重叠。 在该配置中，可以将具有基本上大于插入器的有效面积的组合面积的多个管芯安装在插入器上（并且利用有源区域进行互连）。