公开(公告)号：US08541268B2

公开(公告)日：2013-09-24

申请号：US13315430

申请日：2011-12-09

申请人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu

发明人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66757 ,  H01L29/78603

摘要： A thin film transistor and a method for manufacturing the same are provided. A top-gate thin film transistor is fabricated by a process using two gray-tone photomasks and a lift-off method. Therefore, the method can save cost of photomasks and processes comparing to a conventional fabrication method.

摘要翻译： 提供薄膜晶体管及其制造方法。 顶栅薄膜晶体管通过使用两个灰色光掩模和剥离方法的工艺制造。 因此，与传统的制造方法相比，该方法可以节省光掩模和工艺的成本。

公开(公告)号：US08420420B2

公开(公告)日：2013-04-16

申请号：US13113033

申请日：2011-05-21

申请人： Wei-pang Yen ,  Hsien-kun Chiu ,  Chan-chang Liao ,  Chao-huan Hsu

发明人： Wei-pang Yen ,  Hsien-kun Chiu ,  Chan-chang Liao ,  Chao-huan Hsu

IPC分类号： H01L21/00

CPC分类号： H01L27/1288

摘要： A method of manufacturing a thin film transistor array substrate and a structure of the same are disclosed. The manufacturing method merely requires two steps of mask fabrication to accomplish the manufacture of thin film transistor array, in which the manufacturing method utilizes a first mask fabrication step to define a pattern of a source electrode and a drain electrode of the thin film transistor, and a partially-exposed dielectric layer, and utilizes a second mask fabrication step to define an arrangement of a transparent conductive layer. The manufacturing method and structure can dramatically reduce the manufacturing cost of masks and simplify the whole manufacturing process.

摘要翻译： 公开了制造薄膜晶体管阵列基板的方法及其结构。 该制造方法仅需要两个掩模制造步骤来实现薄膜晶体管阵列的制造，其中制造方法利用第一掩模制造步骤来限定薄膜晶体管的源电极和漏电极的图案，以及 部分曝光的介电层，并且利用第二掩模制造步骤来限定透明导电层的布置。 制造方法和结构可以显着降低面罩的制造成本，简化整个制造过程。

公开(公告)号：US20070269988A1

公开(公告)日：2007-11-22

申请号：US11308872

申请日：2006-05-18

申请人： Ying-Chou Chi ,  Rong-Duo Wang ,  Ying-Tsung Tu ,  Chao-Huan Hsu

发明人： Ying-Chou Chi ,  Rong-Duo Wang ,  Ying-Tsung Tu ,  Chao-Huan Hsu

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76804 ,  H01L21/7685

摘要： The present invention relates to a method for forming a contact opening. First, a substrate having at least a dielectric layer formed thereon is provided. Then, a photoresist layer having a first opening is formed on the dielectric layer. A plasma etching operation is performed to form a second opening in the dielectric layer, and the first opening is located above the second opening. The bottom part of the first opening has a diameter smaller than that of the top part of the second opening. Thereafter, the photoresist layer is removed from the dielectric layer. Accordingly, at least a portion of the exposed contact opening will not be oxidized to prevent an increase in the resistance between the conductive pattern and the conductive layer that fills in the contact opening.

摘要翻译： 本发明涉及形成接触开口的方法。 首先，提供至少形成有介电层的基板。 然后，在电介质层上形成具有第一开口的光致抗蚀剂层。 执行等离子体蚀刻操作以在电介质层中形成第二开口，并且第一开口位于第二开口上方。 第一开口的底部的直径小于第二开口的顶部的直径。 此后，从电介质层去除光致抗蚀剂层。 因此，暴露的接触开口的至少一部分不会被氧化，以防止导电图案和填充在接触开口中的导电层之间的电阻增加。

公开(公告)号：US07294579B1

公开(公告)日：2007-11-13

申请号：US11308872

申请日：2006-05-18

申请人： Ying-Chou Chi ,  Rong-Duo Wang ,  Ying-Tsung Tu ,  Chao-Huan Hsu

发明人： Ying-Chou Chi ,  Rong-Duo Wang ,  Ying-Tsung Tu ,  Chao-Huan Hsu

IPC分类号： H01L21/311

CPC分类号： H01L21/76804 ,  H01L21/7685

摘要： The present invention relates to a method for forming a contact opening. First, a substrate having at least a dielectric layer formed thereon is provided. Then, a photoresist layer having a first opening is formed on the dielectric layer. A plasma etching operation is performed to form a second opening in the dielectric layer, and the first opening is located above the second opening. The bottom part of the first opening has a diameter smaller than that of the top part of the second opening. Thereafter, the photoresist layer is removed from the dielectric layer. Accordingly, at least a portion of the exposed contact opening will not be oxidized to prevent an increase in the resistance between the conductive pattern and the conductive layer that fills in the contact opening.

摘要翻译： 本发明涉及形成接触开口的方法。 首先，提供至少形成有介电层的基板。 然后，在电介质层上形成具有第一开口的光致抗蚀剂层。 执行等离子体蚀刻操作以在电介质层中形成第二开口，并且第一开口位于第二开口上方。 第一开口的底部的直径小于第二开口的顶部的直径。 此后，从电介质层去除光致抗蚀剂层。 因此，暴露的接触开口的至少一部分不会被氧化，以防止导电图案与填充在接触开口中的导电层之间的电阻增加。

公开(公告)号：US20130015445A1

公开(公告)日：2013-01-17

申请号：US13315430

申请日：2011-12-09

申请人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu

发明人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu

IPC分类号： H01L33/08 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66757 ,  H01L29/78603

摘要： A thin film transistor and a method for manufacturing the same are provided. A top-gate thin film transistor is fabricated by a process using two gray-tone photomasks and a lift-off method. Therefore, the method can save cost of photomasks and processes comparing to a conventional fabrication method.

摘要翻译： 提供薄膜晶体管及其制造方法。 顶栅薄膜晶体管通过使用两个灰色光掩模和剥离方法的工艺制造。 因此，与传统的制造方法相比，该方法可以节省光掩模和工艺的成本。

公开(公告)号：US20120261666A1

公开(公告)日：2012-10-18

申请号：US13113033

申请日：2011-05-21

申请人： WEI-PANG YEN ,  Hsien-kun Chiu ,  Chan-chang Liao ,  Chao-huan Hsu

发明人： WEI-PANG YEN ,  Hsien-kun Chiu ,  Chan-chang Liao ,  Chao-huan Hsu

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288

摘要： A method of manufacturing a thin film transistor array substrate and a structure of the same are disclosed. The manufacturing method merely requires two steps of mask fabrication to accomplish the manufacture of thin film transistor array, in which the manufacturing method utilizes a first mask fabrication step to define a pattern of a source electrode and a drain electrode of the thin film transistor, and a partially-exposed dielectric layer, and utilizes a second mask fabrication step to define an arrangement of a transparent conductive layer. The manufacturing method and structure can dramatically reduce the manufacturing cost of masks and simplify the whole manufacturing process.

摘要翻译： 公开了制造薄膜晶体管阵列基板的方法及其结构。 该制造方法仅需要两个掩模制造步骤来实现薄膜晶体管阵列的制造，其中制造方法利用第一掩模制造步骤来限定薄膜晶体管的源电极和漏电极的图案，以及 部分曝光的介电层，并且利用第二掩模制造步骤来限定透明导电层的布置。 制造方法和结构可以显着降低面罩的制造成本，简化整个制造过程。

公开(公告)号：US07943441B2

公开(公告)日：2011-05-17

申请号：US12581153

申请日：2009-10-18

申请人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu ,  Kun-Yuan Huang

发明人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu ,  Kun-Yuan Huang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/78633 ,  H01L29/66757

摘要： A method of forming a thin-film transistor array substrate is provided. A first mask is used to define a source, a drain and a channel on a substrate. A dielectric layer is formed to cover the source, the drain, the channel and the substrate. A second mask is used to define a patterned photoresist and the dielectric layer. A transparent conductive layer is formed to cover the patterned photoresist and the substrate. A lift-off process is performed to remove the patterned photoresist and a portion of the transparent conductive layer disposed on the patterned photoresist. A third mask is used to define a gate disposed on the dielectric layer.

摘要翻译： 提供一种形成薄膜晶体管阵列基板的方法。 第一掩模用于在衬底上限定源极，漏极和沟道。 形成介电层以覆盖源极，漏极，沟道和衬底。 第二掩模用于限定图案化的光致抗蚀剂和介电层。 形成透明导电层以覆盖图案化的光致抗蚀剂和衬底。 执行剥离处理以去除图案化的光致抗蚀剂和设置在图案化光致抗蚀剂上的透明导电层的一部分。 第三掩模用于限定设置在电介质层上的栅极。

公开(公告)号：US20110014753A1

公开(公告)日：2011-01-20

申请号：US12581153

申请日：2009-10-18

申请人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu ,  Kun-Yuan Huang

发明人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu ,  Kun-Yuan Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/78633 ,  H01L29/66757

摘要： A method of forming a thin-film transistor array substrate is provided. A first mask is used to define a source, a drain and a channel on a substrate. A dielectric layer is formed to cover the source, the drain, the channel and the substrate. A second mask is used to define a patterned photoresist and the dielectric layer. A transparent conductive layer is formed to cover the patterned photoresist and the substrate. A lift-off process is performed to remove the patterned photoresist and a portion of the transparent conductive layer disposed on the patterned photoresist. A third mask is used to define a gate disposed on the dielectric layer.

摘要翻译： 提供一种形成薄膜晶体管阵列基板的方法。 第一掩模用于在衬底上限定源极，漏极和沟道。 形成介电层以覆盖源极，漏极，沟道和衬底。 第二掩模用于限定图案化的光致抗蚀剂和介电层。 形成透明导电层以覆盖图案化的光致抗蚀剂和基底。 执行剥离处理以去除图案化的光致抗蚀剂和设置在图案化光致抗蚀剂上的透明导电层的一部分。 第三掩模用于限定设置在电介质层上的栅极。