公开(公告)号：US20130015445A1

公开(公告)日：2013-01-17

申请号：US13315430

申请日：2011-12-09

申请人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu

发明人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu

IPC分类号： H01L33/08 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66757 ,  H01L29/78603

摘要： A thin film transistor and a method for manufacturing the same are provided. A top-gate thin film transistor is fabricated by a process using two gray-tone photomasks and a lift-off method. Therefore, the method can save cost of photomasks and processes comparing to a conventional fabrication method.

摘要翻译： 提供薄膜晶体管及其制造方法。 顶栅薄膜晶体管通过使用两个灰色光掩模和剥离方法的工艺制造。 因此，与传统的制造方法相比，该方法可以节省光掩模和工艺的成本。

公开(公告)号：US08541268B2

公开(公告)日：2013-09-24

申请号：US13315430

申请日：2011-12-09

申请人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu

发明人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L27/1288 ,  H01L27/124 ,  H01L29/66757 ,  H01L29/78603

摘要： A thin film transistor and a method for manufacturing the same are provided. A top-gate thin film transistor is fabricated by a process using two gray-tone photomasks and a lift-off method. Therefore, the method can save cost of photomasks and processes comparing to a conventional fabrication method.

摘要翻译： 提供薄膜晶体管及其制造方法。 顶栅薄膜晶体管通过使用两个灰色光掩模和剥离方法的工艺制造。 因此，与传统的制造方法相比，该方法可以节省光掩模和工艺的成本。

公开(公告)号：US08421096B2

公开(公告)日：2013-04-16

申请号：US13561098

申请日：2012-07-30

申请人： Hsien-Kun Chiu

发明人： Hsien-Kun Chiu

IPC分类号： H01L29/18

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/78633

摘要： A pixel structure and a manufacturing method thereof and a display panel are provided. An electrode material layer, a shielding material layer, an inter-layer dielectric material layer, a semiconductor material layer and a photoresist-layer are sequentially formed on a substrate. The semiconductor material layer, the inter-layer dielectric material layer, the shielding material layer and the electrode material layer are patterned using the photoresist-layer as a mask to form a semiconductor pattern, an inter-layer dielectric pattern, a shielding pattern and a pixel electrode. A source/drain electrically connected to the pixel electrode and covering a portion of the semiconductor pattern is formed on the pixel electrode. A channel is another portion of the semiconductor uncovered by the source/drain. A dielectric layer covering the source/drain, the semiconductor pattern, the inter-layer dielectric pattern, the shielding pattern and the pixel electrode and a gate disposed on the dielectric layer above the channel are formed.

摘要翻译： 提供像素结构及其制造方法和显示面板。 在基板上依次形成电极材料层，屏蔽材料层，层间电介质材料层，半导体材料层和光致抗蚀剂层。 使用光致抗蚀剂层作为掩模对半导体材料层，层间电介质材料层，屏蔽材料层和电极材料层进行构图，以形成半导体图案，层间电介质图案，屏蔽图案和 像素电极。 在像素电极上形成与像素电极电连接并覆盖半导体图案的一部分的源极/漏极。 通道是源极/漏极未覆盖的半导体的另一部分。 形成覆盖源极/漏极，半导体图案，层间电介质图案，屏蔽图案和像素电极的介电层以及设置在沟道上方的电介质层上的栅极。

公开(公告)号：US08420420B2

公开(公告)日：2013-04-16

申请号：US13113033

申请日：2011-05-21

申请人： Wei-pang Yen ,  Hsien-kun Chiu ,  Chan-chang Liao ,  Chao-huan Hsu

发明人： Wei-pang Yen ,  Hsien-kun Chiu ,  Chan-chang Liao ,  Chao-huan Hsu

IPC分类号： H01L21/00

CPC分类号： H01L27/1288

摘要： A method of manufacturing a thin film transistor array substrate and a structure of the same are disclosed. The manufacturing method merely requires two steps of mask fabrication to accomplish the manufacture of thin film transistor array, in which the manufacturing method utilizes a first mask fabrication step to define a pattern of a source electrode and a drain electrode of the thin film transistor, and a partially-exposed dielectric layer, and utilizes a second mask fabrication step to define an arrangement of a transparent conductive layer. The manufacturing method and structure can dramatically reduce the manufacturing cost of masks and simplify the whole manufacturing process.

摘要翻译： 公开了制造薄膜晶体管阵列基板的方法及其结构。 该制造方法仅需要两个掩模制造步骤来实现薄膜晶体管阵列的制造，其中制造方法利用第一掩模制造步骤来限定薄膜晶体管的源电极和漏电极的图案，以及 部分曝光的介电层，并且利用第二掩模制造步骤来限定透明导电层的布置。 制造方法和结构可以显着降低面罩的制造成本，简化整个制造过程。

公开(公告)号：US20120286277A1

公开(公告)日：2012-11-15

申请号：US13561098

申请日：2012-07-30

申请人： Hsien-Kun Chiu

发明人： Hsien-Kun Chiu

IPC分类号： H01L33/16 ,  H01L33/08

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/78633

摘要： A pixel structure and a manufacturing method thereof and a display panel are provided. An electrode material layer, a shielding material layer, an inter-layer dielectric material layer, a semiconductor material layer and a photoresist-layer are sequentially formed on a substrate. The semiconductor material layer, the inter-layer dielectric material layer, the shielding material layer and the electrode material layer are patterned using the photoresist-layer as a mask to form a semiconductor pattern, an inter-layer dielectric pattern, a shielding pattern and a pixel electrode. A source/drain electrically connected to the pixel electrode and covering a portion of the semiconductor pattern is formed on the pixel electrode. A channel is another portion of the semiconductor uncovered by the source/drain. A dielectric layer covering the source/drain, the semiconductor pattern, the inter-layer dielectric pattern, the shielding pattern and the pixel electrode and a gate disposed on the dielectric layer above the channel are formed.

摘要翻译： 提供像素结构及其制造方法和显示面板。 在基板上依次形成电极材料层，屏蔽材料层，层间电介质材料层，半导体材料层和光致抗蚀剂层。 使用光致抗蚀剂层作为掩模对半导体材料层，层间电介质材料层，屏蔽材料层和电极材料层进行构图，以形成半导体图案，层间电介质图案，屏蔽图案和 像素电极。 在像素电极上形成与像素电极电连接并覆盖半导体图案的一部分的源极/漏极。 通道是源极/漏极未覆盖的半导体的另一部分。 形成覆盖源极/漏极，半导体图案，层间电介质图案，屏蔽图案和像素电极的介电层以及设置在沟道上方的电介质层上的栅极。

公开(公告)号：US08263447B2

公开(公告)日：2012-09-11

申请号：US12549370

申请日：2009-08-28

申请人： Hsien-Kun Chiu

发明人： Hsien-Kun Chiu

IPC分类号： H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/78633

摘要： A pixel structure and a manufacturing method thereof and a display panel are provided. An electrode material layer, a shielding material layer, an inter-layer dielectric material layer, a semiconductor material layer and a photoresist-layer are sequentially formed on a substrate. The semiconductor material layer, the inter-layer dielectric material layer, the shielding material layer and the electrode material layer are patterned using the photoresist-layer as a mask to form a semiconductor pattern, an inter-layer dielectric pattern, a shielding pattern and a pixel electrode. A source/drain electrically connected to the pixel electrode and covering a portion of the semiconductor pattern is formed on the pixel electrode. A channel is another portion of the semiconductor uncovered by the source/drain. A dielectric layer covering the source/drain, the semiconductor pattern, the inter-layer dielectric pattern, the shielding pattern and the pixel electrode and a gate disposed on the dielectric layer above the channel are formed.

摘要翻译： 提供像素结构及其制造方法和显示面板。 在基板上依次形成电极材料层，屏蔽材料层，层间电介质材料层，半导体材料层和光致抗蚀剂层。 使用光致抗蚀剂层作为掩模对半导体材料层，层间电介质材料层，屏蔽材料层和电极材料层进行构图，以形成半导体图案，层间电介质图案，屏蔽图案和 像素电极。 在像素电极上形成与像素电极电连接并覆盖半导体图案的一部分的源极/漏极。 通道是源极/漏极未覆盖的半导体的另一部分。 形成覆盖源极/漏极，半导体图案，层间电介质图案，屏蔽图案和像素电极的介电层以及设置在沟道上方的电介质层上的栅极。

公开(公告)号：US20080233739A1

公开(公告)日：2008-09-25

申请号：US11761374

申请日：2007-06-12

申请人： Hsien-Kun Chiu ,  Chin-Chuan Lai ,  Yi-Pen Lin ,  Shu-Chen Yang

发明人： Hsien-Kun Chiu ,  Chin-Chuan Lai ,  Yi-Pen Lin ,  Shu-Chen Yang

IPC分类号： H01L21/44

CPC分类号： H05K3/182 ,  C23C18/1608 ,  C23C18/1653 ,  C25D5/56 ,  H01L21/2885 ,  H01L21/76838 ,  H01L27/124 ,  H05K3/064 ,  H05K2203/0709

摘要： A method for fabricating a conductive layer is provided. First, a substrate is provided and a patterned adhesion layer is formed on the substrate. Next, a chemical plating process is performed to form a first metal layer on the patterned adhesion layer by placing the substrate in an electroplating solution and the electroplating solution is shocked. Thereafter, a second metal layer is formed on the first metal layer by performing a plating process.

摘要翻译： 提供一种制造导电层的方法。 首先，提供基板，并且在基板上形成图案化的粘附层。 接着，进行化学镀处理，通过将基板置于电镀液中而使电镀液被冲击而在图案化的粘合层上形成第一金属层。 此后，通过进行电镀工艺在第一金属层上形成第二金属层。

公开(公告)号：US07943441B2

公开(公告)日：2011-05-17

申请号：US12581153

申请日：2009-10-18

申请人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu ,  Kun-Yuan Huang

发明人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu ,  Kun-Yuan Huang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L29/78633 ,  H01L29/66757

摘要： A method of forming a thin-film transistor array substrate is provided. A first mask is used to define a source, a drain and a channel on a substrate. A dielectric layer is formed to cover the source, the drain, the channel and the substrate. A second mask is used to define a patterned photoresist and the dielectric layer. A transparent conductive layer is formed to cover the patterned photoresist and the substrate. A lift-off process is performed to remove the patterned photoresist and a portion of the transparent conductive layer disposed on the patterned photoresist. A third mask is used to define a gate disposed on the dielectric layer.

摘要翻译： 提供一种形成薄膜晶体管阵列基板的方法。 第一掩模用于在衬底上限定源极，漏极和沟道。 形成介电层以覆盖源极，漏极，沟道和衬底。 第二掩模用于限定图案化的光致抗蚀剂和介电层。 形成透明导电层以覆盖图案化的光致抗蚀剂和衬底。 执行剥离处理以去除图案化的光致抗蚀剂和设置在图案化光致抗蚀剂上的透明导电层的一部分。 第三掩模用于限定设置在电介质层上的栅极。

公开(公告)号：US20110014753A1

公开(公告)日：2011-01-20

申请号：US12581153

申请日：2009-10-18

申请人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu ,  Kun-Yuan Huang

发明人： Chan-Chang Liao ,  Hsien-Kun Chiu ,  Wei-Pang Yen ,  Chao-Huan Hsu ,  Kun-Yuan Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/78633 ,  H01L29/66757

摘要： A method of forming a thin-film transistor array substrate is provided. A first mask is used to define a source, a drain and a channel on a substrate. A dielectric layer is formed to cover the source, the drain, the channel and the substrate. A second mask is used to define a patterned photoresist and the dielectric layer. A transparent conductive layer is formed to cover the patterned photoresist and the substrate. A lift-off process is performed to remove the patterned photoresist and a portion of the transparent conductive layer disposed on the patterned photoresist. A third mask is used to define a gate disposed on the dielectric layer.

摘要翻译： 提供一种形成薄膜晶体管阵列基板的方法。 第一掩模用于在衬底上限定源极，漏极和沟道。 形成介电层以覆盖源极，漏极，沟道和衬底。 第二掩模用于限定图案化的光致抗蚀剂和介电层。 形成透明导电层以覆盖图案化的光致抗蚀剂和基底。 执行剥离处理以去除图案化的光致抗蚀剂和设置在图案化光致抗蚀剂上的透明导电层的一部分。 第三掩模用于限定设置在电介质层上的栅极。

公开(公告)号：US20070231974A1

公开(公告)日：2007-10-04

申请号：US11308494

申请日：2006-03-30

申请人： Hsien-Kun Chiu ,  Yung-Chia Kuan ,  Kuo-Sheng Sun

发明人： Hsien-Kun Chiu ,  Yung-Chia Kuan ,  Kuo-Sheng Sun

IPC分类号： H01L21/84 ,  H01L29/788 ,  H01L21/00

CPC分类号： H01L29/4908 ,  H01L29/66765

摘要： A thin film transistor having a substrate, a bottom layer, a gate, a gate-insulating layer, a channel layer and a source/drain, is provided. The bottom layer is disposed on the substrate. The copper gate is disposed on the bottom layer. The gate-insulating layer covers the copper gate and the bottom layer. The channel layer is disposed on the gate-insulating layer and above the gate. The source/drain is disposed at two sides of the channel layer which is above the gate. By disposing the bottom layer, the problem of poor adhesion between the copper gate and the substrate can be solved.

摘要翻译： 提供了具有基板，底层，栅极，栅极绝缘层，沟道层和源极/漏极的薄膜晶体管。 底层设置在基底上。 铜门设置在底层。 栅极绝缘层覆盖铜栅极和底层。 沟道层设置在栅极绝缘层上并在栅极上方。 源极/漏极设置在栅极上方的沟道层的两侧。 通过设置底层，可以解决铜栅极和衬底之间的粘附性差的问题。