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1.发明授权Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权使用现场可编程门阵列（FPGA）技术与微处理器进行可重配置，指令级硬件加速公开(公告)号：US07603540B2
公开(公告)日：2009-10-13
申请号：US12167202
申请日：2008-07-02
申请人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译： 一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。 以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。 应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。 还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。
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2.发明授权System for using FPGA technology with a microprocessor for reconfigurable, instruction level hardware acceleration 有权使用FPGA技术与微处理器进行可重配置，指令级硬件加速的系统公开(公告)号：US07584345B2
公开(公告)日：2009-09-01
申请号：US10696865
申请日：2003-10-30
申请人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. Doering , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGA in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising thecoprocessor and processor are provided as well.
摘要翻译： 一种用于动态编程现场可编程门阵列的方法（协处理器中的FPGA，耦合到处理器的协处理器）包括：由处理器开始执行应用程序;从处理器接收指令到协处理器以执行应用程序的功能 ;确定协处理器中的FPGA没有用该功能的逻辑编程;获取功能的配置位流;以及使用配置位流编程FPGA，以这种方式，FPGA可以“即时”编程， 即在应用程序的执行过程中动态执行，由FPGA提供的硬件加速和资源共享优势可以被应用程序更频繁地利用，同时提供了包括微处理器和处理器在内的芯片的逻辑灵活性和空间节省。
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公开(公告)号：US07337334B2
公开(公告)日：2008-02-26
申请号：US10367067
申请日：2003-02-14
CPC分类号： G06F1/3203
摘要： A programmable state machine is incorporated into the core of a network processor (NP) to monitor the utilization of different processing elements in the NP and to control the power state of each element as a function of past and predicted utilization. The state machine can be used to control a centralized power management control unit or to control a distributed power management unit where each processing element includes its own state machine. The function of the power management state machine can be implemented in any combination of software and/or hardwired logic, depending on the system design requirements. The monitoring and control are implemented through the use of a power management state change algorithm. The determination of the power state of a processing element accommodates interdependencies between the elements. It also makes adjustments in gain factors in response to actual performance and utilization of the network processor.
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公开(公告)号：US07472293B2
公开(公告)日：2008-12-30
申请号：US11970613
申请日：2008-01-08
CPC分类号： G06F1/3203
摘要： A programmable state machine is incorporated into the core of a network processor (NP) to monitor the utilization of different processing elements in the NP and to control the power state of each element as a function of past and predicted utilization. The state machine can be used to control a centralized power management control unit or to control a distributed power management unit where each processing element includes its own state machine. The function of the power management state machine can be implemented in any combination of software and/or hardwired logic, depending on the system design requirements. The monitoring and control are implemented through the use of a power management state change algorithm. The determination of the power state of a processing element accommodates interdependencies between the elements. It also makes adjustments in gain factors in response to actual performance and utilization of the network processor.
摘要翻译： 可编程状态机被并入到网络处理器（NP）的核心中，以监视NP中不同处理元件的利用率，并且根据过去和预测的利用率来控制每个元件的功率状态。 状态机可用于控制集中式电力管理控制单元或控制分布式电力管理单元，其中每个处理元件包括其自己的状态机。 根据系统设计要求，电源管理状态机的功能可以以软件和/或硬连线逻辑的任意组合来实现。 通过使用电源管理状态变化算法来实现监视和控制。 处理元件的功率状态的确定适应元件之间的相互依赖性。 它还可以根据网络处理器的实际性能和利用率来调整增益因子。
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公开(公告)号：US06191914B1
公开(公告)日：2001-02-20
申请号：US09282718
申请日：1999-03-31
IPC分类号： G11B1704
CPC分类号： G11B17/043
摘要： A compact media drive for use in personal computers has a media support and detector arm structure that ejects to extend external of the drive case at the insertion slot to receive corners of a unit of media during data operations. The arm(s) retract within the drive case or system case when no media is received. This allows a drive case to be proportioned with a drive hub for the media adjacent to the insertion slot to reduce the dimension there between from that for normal full disk insertion. The arm structure permits the drive to collect state information at the rear disk corners necessary to avoid incorrect data operations while a significant portion of the disk remains outside the insertion slot.
摘要翻译： 用于个人计算机的紧凑型介质驱动器具有介质支撑和检测器臂结构，其弹出以在插入槽处延伸驱动器外壳的外部，以在数据操作期间接收介质单元的角。 当没有接收到介质时，手臂在驱动器外壳或系统外壳内缩回。 这允许驱动器壳体与用于与插入槽相邻的介质的驱动轮毂成比例，以减小与正常完全盘插入之间的尺寸。 臂结构允许驱动器收集在后盘盘角落处的状态信息，以避免不正确的数据操作，同时磁盘的大部分保留在插入槽的外部。
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6.发明授权Method and apparatus for distributing control messages between interconnected processing elements by mapping control messages of a shared memory addressable by the receiving processing element 失效用于通过映射可由所述接收处理元件寻址的共享存储器的控制消息来分布互连的处理元件之间的控制消息的方法和装置
公开(公告)号：US5606666A
公开(公告)日：1997-02-25
申请号：US277394
申请日：1994-07-19
申请人： Carl H. Grant , Jace W. Krull , Charles E. Kuhlmann , Shahram Salamian , Eugene M. Thomas , James T. Tsevdos
发明人： Carl H. Grant , Jace W. Krull , Charles E. Kuhlmann , Shahram Salamian , Eugene M. Thomas , James T. Tsevdos
摘要： A computer system is provided in which asynchronously operating processing elements in the system are connected by means of an interconnection media so as to permit communication between an executing program on one of the processing elements with the memory on another processing element. Inter-processing communication logic located on each of the processing elements permits communication between executing programs on any one processing element. Inter-delivery support hardware is provided for interfacing between the interconnection media and the inter-processing communication logic. The inter-delivery support hardware operates asynchronously with respect to the executing programs on the processing elements for (i) enqueuing control elements obtained by a function on a first processing element from physical memory on the first processing element; (ii) temporarily storing the enqueued control elements in a first memory device associated with the first processing element; (iii) copying over the interconnection media via a copy transaction the temporarily stored control elements from the first memory device to a second memory device associated with a second processing element; and (iv) dequeuing the copied control elements from the second memory device to physical memory on the second processing element.
摘要翻译： 提供了一种计算机系统，其中系统中的异步操作处理元件通过互连介质连接，以便允许处理元件之一上的执行程序与另一个处理元件上的存储器之间进行通信。 位于每个处理元件上的处理间通信逻辑允许在任何一个处理元件上执行程序之间的通信。 交互支持硬件被提供用于在互连介质和处理间通信逻辑之间进行接口。 交付支持硬件相对于处理元件上的执行程序异步地操作，用于（i）通过第一处理元件上的物理存储器对通过第一处理元件的功能获得的控制元素进行排队; （ii）将入队控制元件临时存储在与第一处理元件相关联的第一存储器件中; （iii）通过复制事务将临时存储的控制元件从第一存储器设备复制到互连介质到与第二处理元件相关联的第二存储器设备; 以及（iv）将复制的控制元件从第二存储器装置出发到第二处理元件上的物理存储器。
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7.发明申请USING FIELD PROGRAMMABLE GATE ARRAY (FPGA) TECHNOLOGY WITH A MICROPROCESSOR FOR RECONFIGURABLE, INSTRUCTION LEVEL HARDWARE ACCELERATION 有权使用现场可编程门阵列（FPGA）技术与微处理器进行可重新配置，指示级硬件加速公开(公告)号：US20080270754A1
公开(公告)日：2008-10-30
申请号：US12167202
申请日：2008-07-02
申请人： Andreas C. DOERING , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
发明人： Andreas C. DOERING , Silvio Dragone , Andreas Herkersdorf , Richard G. Hofmann , Charles E. Kuhlmann
CPC分类号： G06F9/3877 , G06F9/30181 , G06F9/3897 , G06F15/7867
摘要： A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor to perform a function for the application; determining that the FPGA in the coprocessor is not programmed with logic for the function; fetching a configuration bit stream for the function; and programming the FPGA with the configuration bit stream. In this manner, the FPGA are programmable “on the fly”, i.e., dynamically during the execution of an application. The hardware acceleration and resource sharing advantages provided by the FPGA can be utilized more often by the application. Logic flexibility and space savings on the chip comprising the coprocessor and processor are provided as well.
摘要翻译： 一种用于在协处理器中动态编程现场可编程门阵列（FPGA）的方法，所述协处理器耦合到处理器，所述协处理器包括：由处理器开始执行应用程序; 从所述处理器接收到所述协处理器的指令以执行所述应用的功能; 确定协处理器中的FPGA不是用该功能的逻辑编程的; 获取功能的配置位流; 并使用配置位流对FPGA进行编程。 以这种方式，FPGA可以“即时”编程，即在执行应用期间动态地编程。 应用程序可以更频繁地利用FPGA提供的硬件加速和资源共享优势。 还提供了包括协处理器和处理器的芯片上的逻辑灵活性和空间节省。
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8.发明授权Method and apparatus for arbitrating for a bus to enable split transaction bus protocols 失效用于仲裁总线以实现拆分事务总线协议的方法和装置
公开(公告)号：US5621897A
公开(公告)日：1997-04-15
申请号：US421114
申请日：1995-04-13
IPC分类号： G06F13/362 , G06F13/36
CPC分类号： G06F13/362
摘要： An arrangement and method for arbitration to enable split transaction bus protocols provides for a slave to assert a mask signal that sets a mask bit in a mask register when the slave is not ready to complete a requested transaction. A requesting master is forced off the bus and prevented from re-arbitrating while the mask bit is set in the register. When the slave is ready to complete the transaction, a release master signal is asserted which causes the bit in the shift register to be reset. The requesting master is then able to re-arbitrate for use of the bus to complete the transaction. The usable bandwidth of the bus is increased since other masters are able to arbitrate and use the bus until the slave is ready to complete the transaction with the first requesting master.
摘要翻译： 用于启用拆分事务总线协议的仲裁的布置和方法提供从机在从机未准备好完成所请求的事务时，提供设置掩码寄存器中的掩码位的掩码信号。 请求主机被强制关闭总线，并防止在掩码位置位在寄存器中进行重新仲裁。 当从机准备好完成交易时，断言主信号被断言，这使得移位寄存器中的位被复位。 然后，请求主机能够重新仲裁以使用总线来完成交易。 总线的可用带宽增加，因为其他主机能够仲裁和使用总线，直到从机准备完成与第一请求主机的交易。
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