公开(公告)号：US20050110528A1

公开(公告)日：2005-05-26

申请号：US10707177

申请日：2003-11-25

申请人： Charles Masenas

发明人： Charles Masenas

IPC分类号： H03B5/12 ,  H03C3/00 ,  H03L7/099

CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243

摘要： A structure and associated method for controlling an amplitude of oscillation in a voltage controlled oscillator. The voltage controlled oscillator circuit comprises a drive circuit, an inductor/capacitor (LC) tank circuit, and a diode. The LC tank circuit and the drive circuit collectively comprise a first oscillating node and a second oscillating node. The first oscillating node is adapted to have a first voltage. The second oscillating node is adapted to have a second voltage. The first diode is adapted to control an amplitude of the first voltage and an amplitude of the second voltage.

摘要翻译： 用于控制压控振荡器中的振荡幅度的结构和相关方法。 压控振荡器电路包括驱动电路，电感器/电容器（LC）电路和二极管。 LC槽电路和驱动电路共同包括第一振荡节点和第二振荡节点。 第一振荡节点适于具有第一电压。 第二振荡节点适于具有第二电压。 第一二极管适于控制第一电压的幅度和第二电压的幅度。

公开(公告)号：US20080054963A1

公开(公告)日：2008-03-06

申请号：US11854046

申请日：2007-09-12

申请人： Charles Masenas

发明人： Charles Masenas

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0893

摘要： A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A charge pump is disclosed for providing a charge to a capacitive element on a voltage controlled delay line, wherein the charge is independent of a control voltage step cycle time of the DLL, the charge pump includes: a charge/dump signal generation stage that generates a charge signal and a dump signal during each period of a reference clock signal; a first switched capacitor stage that charges a first capacitor in response to the charge signal and dumps a positive charge from the first capacitor in response to the dump signal; a second switched capacitor stage that charges a second capacitor in response to the charge signal and dumps a negative charge from the second capacitor in response to the dump signal; and an output stage that selectively loads either the positive charge or the negative charge to the capacitive element on the voltage controlled delay line in response to an input signal from a phase detector.

摘要翻译： 具有与DLL的操作频率无关的电荷泵增益的延迟看法循环（DLL）。 公开了一种电荷泵，用于向电压控制的延迟线上的电容元件提供电荷，其中电荷与DLL的控制电压阶跃周期时间无关，电荷泵包括：产生电荷/转储信号的电荷 在参考时钟信号的每个周期期间的充电信号和转储信号; 第一开关电容器级，响应于所述充电信号对第一电容器充电，并且响应于所述转储信号从所述第一电容器转储正电荷; 第二开关电容器级，响应于所述充电信号对第二电容器充电并且响应于所述转储信号从所述第二电容器转移负电荷; 以及输出级，其响应于来自相位检测器的输入信号，有选择地将正电荷或负电荷加载到电压控制延迟线上的电容元件。

公开(公告)号：US20080054962A1

公开(公告)日：2008-03-06

申请号：US11854042

申请日：2007-09-12

申请人： Charles Masenas

发明人： Charles Masenas

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0893

摘要： A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A method for providing a constant gain for a charge pump component of a delay locked loop (DLL) is disclosed, and includes: providing a switched capacitor stage responsive to a charge phase for charging a capacitor and a dump phase for dumping the capacitor; and aligning the charge phase and the dump phase such that a control voltage provided by the charge pump is independent of a frequency of a DLL charge and discharge phase.

摘要翻译： 具有与DLL的操作频率无关的电荷泵增益的延迟看法循环（DLL）。 公开了一种用于为延迟锁定环（DLL）的电荷泵部件提供恒定增益的方法，并且包括：响应于用于对电容器充电的充电阶段和用于倾倒电容器的倾倒相位提供开关电容器级的方法; 并且使电荷相位和倾倒相位对齐，使得由电荷泵提供的控制电压与DLL充电和放电阶段的频率无关。

公开(公告)号：US20070241798A1

公开(公告)日：2007-10-18

申请号：US11279446

申请日：2006-04-12

申请人： Charles Masenas

发明人： Charles Masenas

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/0893

摘要： A delay looked loop (DLL) having a charge pump gain independent of the operating frequency of the DLL. A charge pump is disclosed for providing a charge to a capacitive element on a voltage controlled delay line, wherein the charge is independent of a control voltage step cycle time of the DLL, the charge pump includes: a charge/dump signal generation stage that generates a charge signal and a dump signal during each period of a reference clock signal; a first switched capacitor stage that charges a first capacitor in response to the charge signal and dumps a positive charge from the first capacitor in response to the dump signal; a second switched capacitor stage that charges a second capacitor in response to the charge signal and dumps a negative charge from the second capacitor in response to the dump signal; and an output stage that selectively loads either the positive charge or the negative charge to the capacitive element on the voltage controlled delay line in response to an input signal from a phase detector.

摘要翻译： 具有与DLL的操作频率无关的电荷泵增益的延迟看法循环（DLL）。 公开了一种电荷泵，用于向电压控制的延迟线上的电容元件提供电荷，其中电荷与DLL的控制电压阶跃周期时间无关，电荷泵包括：产生电荷/转储信号的电荷 在参考时钟信号的每个周期期间的充电信号和转储信号; 第一开关电容器级，响应于所述充电信号对第一电容器充电，并且响应于所述转储信号从所述第一电容器转储正电荷; 第二开关电容器级，响应于所述充电信号对第二电容器充电并且响应于所述转储信号从所述第二电容器转移负电荷; 以及输出级，其响应于来自相位检测器的输入信号，有选择地将正电荷或负电荷加载到电压控制延迟线上的电容元件。

公开(公告)号：US20070222488A1

公开(公告)日：2007-09-27

申请号：US11757510

申请日：2007-06-04

申请人： Anthony Bonaccio ,  Charles Masenas ,  Troy Seman

发明人： Anthony Bonaccio ,  Charles Masenas ,  Troy Seman

IPC分类号： H03L7/00

CPC分类号： H03L7/081 ,  H04L7/033

摘要： A clock and data recovery circuit including: means for generating a first and a second clock signal; means for receiving the first clock signal and for generating a third clock signal from the first clock signal and means for receiving the second clock signal and for generating a fourth clock signal, wherein at least one of the third and the fourth clock signals differ in phase from the first and the second clock signal respectively; means for receiving the third and fourth clock signals and a serial data stream and for generating a reconstructed serial data stream and a phase error signal; means for receiving the phase error signal and for generating a phase adjustment signal and means for receiving the phase adjustment signal by the by the clock generation circuit in a feedback loop to adjust the phases of the first and second clock signals.

摘要翻译： 一种时钟和数据恢复电路，包括：用于产生第一和第二时钟信号的装置; 用于接收第一时钟信号并用于从第一时钟信号产生第三时钟信号的装置，以及用于接收第二时钟信号并产生第四时钟信号的装置，其中第三和第四时钟信号中的至少一个在相位上是不同的 分别从第一和第二时钟信号; 用于接收第三和第四时钟信号和串行数据流并用于产生重建的串行数据流和相位误差信号的装置; 用于接收相位误差信号并产生相位调整信号的装置，以及用于在反馈回路中由时钟产生电路接收相位调整信号的装置，以调整第一和第二时钟信号的相位。

公开(公告)号：US20060189294A1

公开(公告)日：2006-08-24

申请号：US11410829

申请日：2006-04-24

申请人： Kenneth Goodnow ,  Riyon Harding ,  Charles Masenas ,  Jason Norman ,  Sebastian Ventrone

发明人： Kenneth Goodnow ,  Riyon Harding ,  Charles Masenas ,  Jason Norman ,  Sebastian Ventrone

IPC分类号： H04B1/28

CPC分类号： H04B1/38

摘要： A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the transmission of data from other cores. Both transmitter circuitry and receiver circuitry may include of a phase-locked loop circuit having a voltage-controlled oscillator. Each core may transmit and receive data on a unique frequency with respect to other cores embedded in an integrated circuit on a silicon chip or transmit and receive data on the same frequency as other cores embedded in an integrated circuit on a silicon chip. Groups of cores may share transmitter and receiver circuitry.

摘要翻译： 一种用于在嵌入在硅芯片上的集成电路中的核之间传输数据的通信系统。 通信系统包括用于在核心和接收机电路之间无线地传输数据的发射机电路，用于无线地接收来自其他核的数据传输。 发射机电路和接收机电路都可以包括具有压控振荡器的锁相环电路。 每个核心可以相对于嵌入在硅芯片上的集成电路中的其它核心以独特的频率发送和接收数据，或者以与嵌入在硅芯片上的集成电路中的其它芯片相同的频率发送和接收数据。 核心组可以共享发射机和接收机电路。

公开(公告)号：US20050275476A1

公开(公告)日：2005-12-15

申请号：US10709811

申请日：2004-05-28

申请人： John Austin ,  Melissa Beacom ,  Charles Masenas

发明人： John Austin ,  Melissa Beacom ,  Charles Masenas

IPC分类号： H03B1/00 ,  H03K3/012 ,  H03K3/03

CPC分类号： H03K3/012 ,  H03K3/0315

摘要： A voltage-controlled oscillator (VCO) comprising an odd number of delay stage circuits. Each delay stage circuit operates between supply voltages VDD and VSS (VDD>VSS) and comprises (1) an input node, (2) an output node, (3) an inverting circuit, and (4) an electric discharge path coupling the output node to VSS. The electric discharge path includes a switch circuit and a resistance adjusting circuit electrically coupled in series between the output node and VSS. In response to an input signal rising at the input node, the inverting circuit decreases an output signal at the output node, and the electric discharge path opens to help pull the output signal down faster. In response to an input signal falling at the input node, the inverting circuit increases the output signal at the output node, and the electric discharge path closes to minimize its own effect.

摘要翻译： 包括奇数个延迟级电路的压控振荡器（VCO）。 每个延迟级电路在电源电压VDD和VSS（VDD> VSS）之间工作，并且包括（1）输入节点，（2）输出节点，（3）反相电路，以及（4）将输出 节点到VSS。 放电路径包括在输出节点和VSS之间串联电耦合的开关电路和电阻调节电路。 响应于在输入节点处上升的输入信号，反相电路减小输出节点处的输出信号，并且放电路径打开以帮助较快地拉出输出信号。 响应于在输入节点处的输入信号，反相电路增加输出节点处的输出信号，并且放电路径关闭以最小化其自身的效果。