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1.发明申请SIGNAL DELAY APPARATUS FOR PROVIDING EXACT DELAY AMOUNT, MEMORY APPARATUS UTILIZING THE SIGNAL DELAY APPARATUS, AND SIGNAL DELAY METHOD 有权用于提供精确延迟量的信号延迟装置，使用信号延迟装置的记忆装置和信号延迟方法公开(公告)号：US20120194242A1
公开(公告)日：2012-08-02
申请号：US13015595
申请日：2011-01-28
申请人： Yen-Yin Huang , Chih-Hsien Lin , Chauo-Min Chen , Ming-Shih Yu
发明人： Yen-Yin Huang , Chih-Hsien Lin , Chauo-Min Chen , Ming-Shih Yu
CPC分类号： H03L7/0816 , H03K5/133 , H03K5/135 , H03L7/0814
摘要： A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.
摘要翻译： 一种信号延迟装置，包括：周期数字化电路，用于对参考时钟信号的周期进行数字化以产生数字化参考周期; 延迟控制信号发生器，用于根据数字化参考周期产生延迟控制信号，参考频率和所需延迟指示信号; 以及延迟电路，用于根据所需的延迟控制信号延迟输入信号以产生输出信号。
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2.发明授权Signal delay apparatus for providing exact delay amount, memory apparatus utilizing the signal delay apparatus, and signal delay method 有权用于提供精确延迟量的信号延迟装置，利用信号延迟装置的存储装置和信号延迟方法公开(公告)号：US08242824B1
公开(公告)日：2012-08-14
申请号：US13015595
申请日：2011-01-28
申请人： Yen-Yin Huang , Chih-Hsien Lin , Chauo-Min Chen , Ming-Shih Yu
发明人： Yen-Yin Huang , Chih-Hsien Lin , Chauo-Min Chen , Ming-Shih Yu
IPC分类号： H03L7/00
CPC分类号： H03L7/0816 , H03K5/133 , H03K5/135 , H03L7/0814
摘要： A signal delay apparatus, including: a period digitalization circuit, for digitalizing a period of a reference clock signal to generate a digitalized reference period; a delay control signal generator, for generating a delay control signal according to the digitalized reference period, a reference frequency and a required delay indicating signal; and a delay circuit, for delaying an input signal to generate an output signal according to the required delay control signal.
摘要翻译： 一种信号延迟装置，包括：周期数字化电路，用于对参考时钟信号的周期进行数字化以产生数字化参考周期; 延迟控制信号发生器，用于根据数字化参考周期产生延迟控制信号，参考频率和所需延迟指示信号; 以及延迟电路，用于根据所需的延迟控制信号延迟输入信号以产生输出信号。
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3.发明授权公开(公告)号：US08724762B2
公开(公告)日：2014-05-13
申请号：US13175884
申请日：2011-07-04
申请人： Yen-Yin Huang , Chauo-Min Chen , Kuan-Yu Chen , Yu-Sheng Yi , Ming-Shih Yu
发明人： Yen-Yin Huang , Chauo-Min Chen , Kuan-Yu Chen , Yu-Sheng Yi , Ming-Shih Yu
IPC分类号： H04L7/00
摘要： A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.
摘要翻译： 一种用于产生由接收器/收发器/收发器/收发器系统使用的时钟信号的时钟再生方法包括：对至少一个输入信号执行数据/模式检测以产生恢复的数据; 根据同步模式规则检测所述输入信号中的至少一个同步模式，并产生与所述同步模式对应的同步信号; 对该同步信号进行频率锁定，生成时钟信号。 更具体地，根据同步模式规则检测输入信号中的至少一个同步模式的步骤还包括：通过对恢复的数据执行同步模式检测来检测至少一个同步模式。 还提供了相关联的无参考接收器和相关联的无晶体系统。
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4.发明申请公开(公告)号：US20130010909A1
公开(公告)日：2013-01-10
申请号：US13175884
申请日：2011-07-04
申请人： Yen-Yin Huang , Chauo-Min Chen , Kuan-Yu Chen , Yu-Sheng Yi , Ming-Shih Yu
发明人： Yen-Yin Huang , Chauo-Min Chen , Kuan-Yu Chen , Yu-Sheng Yi , Ming-Shih Yu
IPC分类号： H04L7/00
摘要： A clock regeneration method, for generating a clock signal for being utilized by a receiver/transceiver/receiver system/transceiver system, includes: performing data/pattern detection on at least one input signal to generate recovered data; detecting at least one synchronization pattern in the input signal according to a synchronization pattern rule, and generating a synchronization signal corresponding to the synchronization pattern; and performing frequency-locking on the synchronization signal to generate the clock signal. More particularly, the step of detecting the at least one synchronization pattern in the input signal according to the synchronization pattern rule further comprises: detecting the at least one synchronization pattern by performing synchronization pattern detection on the recovered data. An associated reference-less receiver and an associated crystal-less system are also provided.
摘要翻译： 一种用于产生由接收器/收发器/收发器/收发器系统使用的时钟信号的时钟再生方法包括：对至少一个输入信号执行数据/模式检测以产生恢复的数据; 根据同步模式规则检测所述输入信号中的至少一个同步模式，并产生与所述同步模式对应的同步信号; 对该同步信号进行频率锁定，生成时钟信号。 更具体地，根据同步模式规则检测输入信号中的至少一个同步模式的步骤还包括：通过对恢复的数据执行同步模式检测来检测至少一个同步模式。 还提供了相关联的无参考接收器和相关联的无晶体系统。
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