公开(公告)号：US20140023129A1

公开(公告)日：2014-01-23

申请号：US13997075

申请日：2012-03-30

Applicant: Chee Hong Aw

Inventor： Chee Hong Aw

IPC: H03G3/34

CPC classification number: H03G3/341 ,  H03K5/1532 ,  H03K5/24 ,  H04L25/0276

Abstract: A squelch detector includes is configured to receive a time-varying differential communication signal, and includes switched capacitors and an inverter configured to provide an indication of whether a level of the received communication signal is above or below a threshold value.

Abstract translation: 静噪检测器装置被配置为接收时变差分通信信号，并且包括开关电容器和被配置为提供所接收的通信信号的电平是否高于或低于阈值的指示的反相器。

公开(公告)号：US08397096B2

公开(公告)日：2013-03-12

申请号：US12785047

申请日：2010-05-21

Applicant: Sergey Shumarayev ,  Edwin Yew Fatt Kok ,  Lip Kai Soh ,  Chee Hong Aw ,  Tee Wee Tan

Inventor： Sergey Shumarayev ,  Edwin Yew Fatt Kok ,  Lip Kai Soh ,  Chee Hong Aw ,  Tee Wee Tan

IPC: G06F1/00 ,  G06F1/04 ,  G06F13/14

CPC classification number: H03L7/0805 ,  H03K19/1774 ,  H03K19/17744 ,  H03L7/0891 ,  H03L7/095

Abstract: An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.

Abstract translation: 集成电路包括物理介质连接（PMA）电路，其包括用于串行数据信号的两种不同类型的收发信道。 一种收发信道用于收发相对低速的串行数据信号。 另一种收发器通道适用于收发相对高速的串行数据信号。 高速通道可用作锁相环（PLL）电路，用于提供时钟信号以供其他高速和/或低速通道使用。 低速通道也可以从单独的低速PLL电路获取时钟信号。

公开(公告)号：US20160380622A1

公开(公告)日：2016-12-29

申请号：US14748840

申请日：2015-06-24

Applicant: Chee Hong Aw

Inventor： Chee Hong Aw

IPC: H03K3/356 ,  G11C7/10 ,  H03K3/037

CPC classification number: H03K3/356113 ,  G11C7/065 ,  G11C7/1084 ,  G11C7/1087 ,  H03K3/037 ,  H03K3/356139 ,  H03K3/356191 ,  H03K5/249

Abstract: Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair of input transistors, the first pair of transistors including gates coupled to the input nodes, a second stage including a second pair of input transistors, the second pair of transistors including gates coupled to the input nodes, and a third stage including inverters coupled to the output nodes. The inverters are coupled to the first and second stages at the same nodes to switch the output signals between different voltages based on the input signals.

Abstract translation: 一些实施例包括具有输入节点以接收输入信号的装置，输出节点以提供输出信号，第一级包括第一对输入晶体管，第一对晶体管包括耦合到输入节点的栅极，第二级包括第二对 的第二对晶体管，包括耦合到输入节点的栅极，以及包括耦合到输出节点的反相器的第三级。 逆变器在相同的节点处耦合到第一和第二级，以基于输入信号来切换不同电压之间的输出信号。

公开(公告)号：US20150214723A1

公开(公告)日：2015-07-30

申请号：US14163806

申请日：2014-01-24

Applicant: Chee Hong AW

Inventor： Chee Hong AW

IPC: H02H3/20

CPC classification number: H02H3/20 ,  H02H1/0007 ,  H02H3/202 ,  H03K3/02337

Abstract: Described is an apparatus which comprises a pass-gate; and a control unit to control gate terminal of the pass-gate according to first availability of first or second power supplies, the control unit including: a voltage detector to detect the second power supply; and a supply switching circuit to generate a local supply for controlling the gate terminal of the pass-gate according to an output of the voltage detector.

Abstract translation: 描述了一种包括通过门的装置; 以及控制单元，用于根据第一或第二电源的第一可用性来控制所述通孔的栅极端子，所述控制单元包括：电压检测器，用于检测所述第二电源; 以及电源切换电路，用于根据电压检测器的输出产生用于控制通过栅极的栅极端子的本地电源。

公开(公告)号：US09093971B2

公开(公告)日：2015-07-28

申请号：US13997075

申请日：2012-03-30

Applicant: Chee Hong Aw

Inventor： Chee Hong Aw

IPC: H03G3/34 ,  H04L25/02

CPC classification number: H03G3/341 ,  H03K5/1532 ,  H03K5/24 ,  H04L25/0276

Abstract: A squelch detector includes is configured to receive a time-varying differential communication signal, and includes switched capacitors and an inverter configured to provide an indication of whether a level of the received communication signal is above or below a threshold value.

Abstract translation: 静噪检测器装置被配置为接收时变差分通信信号，并且包括开关电容器和被配置为提供所接收的通信信号的电平是否高于或低于阈值的指示的反相器。

公开(公告)号：US20110285434A1

公开(公告)日：2011-11-24

申请号：US12785047

申请日：2010-05-21

Applicant: Sergey Shumarayev ,  Edwin Yew Fatt Kok ,  Lip Kai Soh ,  Chee Hong Aw ,  Tee Wee Tan

Inventor： Sergey Shumarayev ,  Edwin Yew Fatt Kok ,  Lip Kai Soh ,  Chee Hong Aw ,  Tee Wee Tan

IPC: H03L7/06

CPC classification number: H03L7/0805 ,  H03K19/1774 ,  H03K19/17744 ,  H03L7/0891 ,  H03L7/095

Abstract: An integrated circuit includes physical media attachment (“PMA”) circuitry that includes two different kinds of transceiver channels for serial data signals. One kind of transceiver channel is adapted for transceiving relatively low-speed serial data signals. The other kind of transceiver channel is adapted for transceiving relatively high-speed serial data signals. A high-speed channel is alternatively usable as phase-locked loop (“PLL”) circuitry for providing a clock signal for use by other high- and/or low-speed channels. A low-speed channel can alternatively get a clock signal from separate low-speed PLL circuitry.

Abstract translation: 集成电路包括物理介质连接（“PMA”）电路，其包括用于串行数据信号的两种不同类型的收发信道。 一种收发信道用于收发相对低速的串行数据信号。 另一种收发器通道适用于收发相对高速的串行数据信号。 高速通道可用作锁相环（“PLL”）电路，用于提供其它高速和/或低速通道使用的时钟信号。 低速通道也可以从单独的低速PLL电路获取时钟信号。