公开(公告)号：US20080157379A1

公开(公告)日：2008-07-03

申请号：US11980649

申请日：2007-10-31

申请人： Chee Hong Choi

发明人： Chee Hong Choi

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76831

摘要： A method for fabricating a semiconductor device having a metal wiring is provided. The method includes: forming an inter-metal dielectric (IMD) layer on the semiconductor substrate having a first metal wiring formed therein, the IMD layer including a first IMD layer and a second IMD layer; forming a via hole in the IMD layer to expose the first metal wiring; forming an ion barrier layer on sidewalls of the via hole; forming a diffusion barrier layer on the semiconductor substrate, on which the ion barrier layer has been formed; forming a metal layer on the semiconductor substrate in the via hole; and forming a second metal wiring on the semiconductor substrate, the second metal wiring contacting the metal layer in the via hole.

摘要翻译： 提供一种制造具有金属布线的半导体器件的方法。 该方法包括：在其上形成有第一金属布线的半导体衬底上形成金属间电介质（IMD）层，IMD层包括第一IMD层和第二IMD层; 在IMD层中形成通孔以露出第一金属布线; 在所述通孔的侧壁上形成离子阻挡层; 在其上形成有离子阻挡层的半导体衬底上形成扩散阻挡层; 在所述通孔中在所述半导体衬底上形成金属层; 以及在所述半导体衬底上形成第二金属布线，所述第二金属布线与所述通孔中的所述金属层接触。

公开(公告)号：US07314831B2

公开(公告)日：2008-01-01

申请号：US11201203

申请日：2005-08-11

申请人： Chee Hong Choi

发明人： Chee Hong Choi

IPC分类号： H01L21/302

CPC分类号： H01L21/7684 ,  H01L21/76829

摘要： A copper line on a semiconductor device and a method for forming the same is disclosed, wherein an insulating layer is deposited so as to minimize the dishing of IMD without using a dummy area when performing the planarization process. The method of forming the copper line on the semiconductor device includes the steps of forming an IMD on a semiconductor substrate including a lower metal layer, forming an isolation layer on the IMD, exposing the lower metal layer by patterning the IMD and the isolation layer, forming a copper layer on the exposed lower metal layer and the isolation layer, and planarizing the copper layer.

摘要翻译： 公开了一种半导体器件上的铜线及其形成方法，其中淀积绝缘层，以便在进行平坦化处理时不使用虚拟区域来最小化IMD的凹陷。 在半导体器件上形成铜线的方法包括以下步骤：在包括下金属层的半导体衬底上形成IMD，在IMD上形成隔离层，通过图案化IMD和隔离层露出下金属层; 在暴露的下金属层和隔离层上形成铜层，并平坦化铜层。

公开(公告)号：US07307000B2

公开(公告)日：2007-12-11

申请号：US11367325

申请日：2006-03-06

申请人： Chee Hong Choi

发明人： Chee Hong Choi

IPC分类号： H01L21/20

CPC分类号： H01L28/60 ,  H01L21/76802 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor for a semiconductor device includes a first inter metal dielectric layer is disposed on a substrate. A first electrode is disposed on the first inter metal dielectric layer. A second electrode partially overlaps the first electrode. A first dielectric layer is disposed between the first and second electrodes. A third electrode partially overlaps the second electrode. A second dielectric layer is disposed between the second and third electrodes. An etch stop layer is disposed on the first, second, and third electrodes. A second inter metal dielectric layer is formed on the etch stop layer and includes first, second, and third via holes exposing the first and third electrodes and the etch stop layer. First, second, and third plugs are disposed in the first, second, and third via holes.

摘要翻译： 一种用于半导体器件的电容器包括：第一金属间介电层设置在基板上。 第一电极设置在第一金属间介电层上。 第二电极与第一电极部分重叠。 第一电介质层设置在第一和第二电极之间。 第三电极与第二电极部分重叠。 第二电介质层设置在第二和第三电极之间。 蚀刻停止层设置在第一，第二和第三电极上。 第二金属介电层形成在蚀刻停止层上，并且包括暴露第一和第三电极和蚀刻停止层的第一，第二和第三通孔。 第一，第二和第三插头设置在第一，第二和第三通孔中。

公开(公告)号：US07265026B2

公开(公告)日：2007-09-04

申请号：US11024517

申请日：2004-12-28

申请人： Chee Hong Choi

发明人： Chee Hong Choi

IPC分类号： H01L21/76

CPC分类号： H01L21/76235

摘要： An isolation method in a semiconductor device is disclosed. The example method sequentially forms a pad oxide layer and a pad nitride layer on a semiconductor substrate, patterns the pad nitride and oxide layers to form an opening exposing a portion of the substrate, and forms a trench in exposed portion of the substrate. The example method also etches the patterned pad nitride layer to extend the opening, carries out SAC oxidation on the extended opening and the trench to provide a rounded corner to an upper corner of the substrate in the vicinity of the trench, and fills the trench with an insulating layer.

摘要翻译： 公开了半导体器件中的隔离方法。 该示例性方法在半导体衬底上顺序地形成焊盘氧化物层和衬垫氮化物层，对焊盘氮化物和氧化物层进行图案化以形成暴露衬底的一部分的开口，并在衬底的暴露部分形成沟槽。 示例性方法还蚀刻图案化衬垫氮化物层以延伸开口，在延伸的开口和沟槽上执行SAC氧化，以在沟槽附近向衬底的上角提供圆角，并且用沟槽填充沟槽 绝缘层。

公开(公告)号：US07259098B2

公开(公告)日：2007-08-21

申请号：US10747599

申请日：2003-12-29

申请人： Seok Su Kim ,  Chee Hong Choi

发明人： Seok Su Kim ,  Chee Hong Choi

IPC分类号： H01L21/302

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324

摘要： Semiconductor devices and methods for fabricating a semiconductor devices are disclosed. A disclosed method comprises: forming a first gate electrode functioning as a flash memory; forming first spacers on sidewalls of the first gate electrode; forming a second gate electrode functioning as a normal gate electrode; forming a source/drain region with a shallow junction by performing a first ion implantation process using at least one of the first spacers as a mask; forming second spacers on a sidewall of the first spacer and on sidewalls of the second gate electrode; forming a source/drain region with a deep junction by performing a second ion implantation process using the second spacers as a mask.

摘要翻译： 公开了用于制造半导体器件的半导体器件和方法。 所公开的方法包括：形成用作闪存的第一栅电极; 在所述第一栅电极的侧壁上形成第一间隔物; 形成用作正常栅电极的第二栅电极; 通过使用所述第一间隔物中的至少一个作为掩模执行第一离子注入工艺来形成具有浅结的源极/漏极区域; 在所述第一间隔物的侧壁和所述第二栅电极的侧壁上形成第二间隔物; 通过使用第二间隔物作为掩模进行第二离子注入工艺，形成具有深结的源极/漏极区域。

公开(公告)号：US20070152228A1

公开(公告)日：2007-07-05

申请号：US11614730

申请日：2006-12-21

申请人： Chee Hong Choi

发明人： Chee Hong Choi

IPC分类号： H01L33/00

CPC分类号： H01L27/14685 ,  H01L27/14621 ,  H01L27/14627

摘要： A CMOS image sensor may include at least one of: a semiconductor substrate over which a photodiode and transistors are formed; passivation layers formed over a semiconductor substrate; and color PRs buried in trenches formed in the passivation layers and formed to be higher than the trenches.

摘要翻译： CMOS图像传感器可以包括以下至少一个：半导体衬底，在其上形成光电二极管和晶体管; 形成在半导体衬底上的钝化层; 以及掩埋在形成于钝化层中的沟槽中并形成为高于沟槽的彩色PR。

公开(公告)号：US20070145492A1

公开(公告)日：2007-06-28

申请号：US11608635

申请日：2006-12-08

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76855 ,  H01L21/76858 ,  H01L23/485 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a semiconductor device includes forming an insulating layer over the semiconductor substrate and the gate electrode. An insulating layer may have a via hole connected to the semiconductor substrate or the gate electrode and a trench connected to the via hole. A first barrier layer and a second barrier layer may be formed. The first barrier layer and the second barrier layer may be annealed to form a silicide and combine the first barrier layer and the second barrier layer to form a metal compound.

摘要翻译： 制造半导体器件的方法包括在半导体衬底和栅电极上形成绝缘层。 绝缘层可以具有连接到半导体衬底或栅电极的通孔以及连接到通孔的沟槽。 可以形成第一阻挡层和第二阻挡层。 第一阻挡层和第二阻挡层可以退火以形成硅化物，并且组合第一阻挡层和第二阻挡层以形成金属化合物。

公开(公告)号：US08325262B2

公开(公告)日：2012-12-04

申请号：US12326902

申请日：2008-12-03

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H04N3/14 ,  H04N5/335

CPC分类号： H04N5/217 ,  H01L27/14603 ,  H01L27/14605 ,  H01L27/14689

摘要： An image sensor and a manufacturing method for an image sensor. An image may include a central pixel array that contains pixels disposed in a center of a pixel area, and a peripheral pixel array that contains pixels disposed in a periphery of the pixel area. A gate oxide layer at a center area of a photodiode may have a smaller thickness than a gate oxide layer of pixels at a center area of the photodiode.

摘要翻译： 图像传感器和图像传感器的制造方法。 图像可以包括包含设置在像素区域的中心的像素的中心像素阵列，以及包含设置在像素区域的周边中的像素的外围像素阵列。 在光电二极管的中心区域的栅氧化层可以具有比光电二极管的中心区域处的像素的栅氧化层更薄的厚度。

公开(公告)号：US20090267237A1

公开(公告)日：2009-10-29

申请号：US12497856

申请日：2009-07-06

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L23/48

CPC分类号： H01L21/76808 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device includes forming an insulation film over a semiconductor substrate having a conduction layer; forming a trench pattern over the insulation film; etching an upper portion of the insulation film by using the trench pattern as a mask to form a trench; removing the trench pattern; forming a spacer film over the insulation film having the trench; etching the space film to form a spacer by using a blanket etching process, the spacer remaining over an edge of an inner portion of the trench; etching the insulation film to form a via hole by using as a mask the spacer; completely removing the spacer; forming a barrier film over sidewalls of the trench and the via hole; and forming a metal line with which fills inner portions of the trench and the via hole.

摘要翻译： 一种制造半导体器件的方法包括在具有导电层的半导体衬底上形成绝缘膜; 在绝缘膜上形成沟槽图案; 通过使用沟槽图案作为掩模蚀刻绝缘膜的上部以形成沟槽; 去除沟槽图案; 在具有沟槽的绝缘膜上形成间隔膜; 通过使用覆盖蚀刻工艺蚀刻空间膜以形成间隔物，间隔物保留在沟槽的内部的边缘上; 通过使用间隔物作为掩模蚀刻绝缘膜以形成通孔; 完全去除垫片; 在所述沟槽和所述通孔的侧壁上形成阻挡膜; 并且形成填充沟槽和通孔的内部的金属线。

公开(公告)号：US20090140303A1

公开(公告)日：2009-06-04

申请号：US12326905

申请日：2008-12-03

申请人： Chee-Hong Choi

发明人： Chee-Hong Choi

IPC分类号： H01L23/535 ,  H01L21/4763 ,  H01L21/443

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method for manufacturing the same includes forming a via pattern having a matrix form in a dielectric layer. The via pattern includes a via slit provided at the center of the via pattern and a plurality of via holes provided at an outer periphery of the via pattern and surrounding the via slit. Metal plugs are formed in the via holes.

摘要翻译： 半导体器件及其制造方法包括在电介质层中形成具有矩阵形式的通孔图案。 通孔图案包括设置在通孔图案的中心处的通孔狭缝和设置在通孔图案的外周并围绕通孔狭缝的多个通孔。 金属塞形成在通孔中。