Abstract:
Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.
Abstract:
An information exchange method includes steps of shaking a first electronic device and a second electronic device simultaneously; recording a first vibration waveform of the first electronic device and recording a second vibration waveform of the second electronic device; determining whether the first vibration waveform and the second vibration waveform match each other; and transmitting a first information related to the first electronic device to the second electronic device when the first vibration waveform and the second vibration waveform match each other.
Abstract:
Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.
Abstract:
An information exchange method includes steps of shaking a first electronic device and a second electronic device simultaneously; recording a first vibration waveform of the first electronic device and recording a second vibration waveform of the second electronic device; determining whether the first vibration waveform and the second vibration waveform match each other; and transmitting a first information related to the first electronic device to the second electronic device when the first vibration waveform and the second vibration waveform match each other.
Abstract:
The present invention relates to a separation type pneumatic dual partition membrane pump, which comprises a pump body and an external pneumatic control valve which is separately installed. Through the operation of the external pneumatic control valve, the main shaft of the pump body and the valve rod of the external pneumatic control valve are reciprocally moved, and the two partition membranes respectively generate stretch and compress motions for changing the volume of each liquid room in the pump body so as to perform the pump stroke and the liquid suction stroke to the liquid.
Abstract:
The invention provides a classifying method for digital images. First, a discrete cosine transform is performed on a candidate area of a digital image to generate a set of discrete cosine transform coefficients. Then, a set of texture parameters is generated based on the set of discrete cosine transform coefficients. At last, a classified result of the digital image is generated based on the set of texture parameters.
Abstract:
A method of fabricating a non-volatile memory device is provided. The method includes forming a plurality of trenches in a substrate. The trenches are filled with first conducting layers to serve as buried bit lines. Thereafter, a charge storage layer is formed on the substrate to cover the surface of the substrate and the first conducting layers. A plurality of second conducting layers is formed on the charge storage layer to serve as word lines.