公开(公告)号：US08044724B2

公开(公告)日：2011-10-25

申请号：US12430430

申请日：2009-04-27

申请人： Chethan Rao ,  Alvin Wang ,  Shaishav Desai

发明人： Chethan Rao ,  Alvin Wang ,  Shaishav Desai

IPC分类号： H03L7/00

CPC分类号： H03L7/099 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1075 ,  H03L7/183

摘要： The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

摘要翻译： 本发明涉及用于生成用于多速时钟应用的低抖动大频率调谐基于LC的锁相环电路的系统和/或方法。 除了多个降噪功能之外，锁相环包括可实现宽环路带宽的可编程电荷泵和环路滤波器，能够实现宽VCO频率范围的可编程VCO和进一步实现宽范围的每通道时钟分频器 PLL频率范围。 此外，自动校准电路确保PLL中包含的VCO接收用于VCO频率范围内降噪的最佳电流。

公开(公告)号：US20100073051A1

公开(公告)日：2010-03-25

申请号：US12430430

申请日：2009-04-27

申请人： Chethan Rao ,  Alvin Wang ,  Shaishav Desai

发明人： Chethan Rao ,  Alvin Wang ,  Shaishav Desai

IPC分类号： H03L7/06

CPC分类号： H03L7/099 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/1075 ,  H03L7/183

摘要： ABSTRACT The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

摘要翻译： 摘要本发明涉及用于生成用于多速时钟应用的低抖动大频率调谐基于LC的锁相环电路的系统和/或方法。 除了多个降噪功能之外，锁相环包括可实现宽环路带宽的可编程电荷泵和环路滤波器，能够实现宽VCO频率范围的可编程VCO和进一步实现宽范围的每通道时钟分频器 PLL频率范围。 此外，自动校准电路确保PLL中包含的VCO接收用于VCO频率范围内降噪的最佳电流。

公开(公告)号：US20130076450A1

公开(公告)日：2013-03-28

申请号：US13244254

申请日：2011-09-23

申请人： Chethan Rao ,  Shaishav Desai ,  Alvin Wang

发明人： Chethan Rao ,  Shaishav Desai ,  Alvin Wang

IPC分类号： H03L7/08

CPC分类号： H03L7/183 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/104 ,  H03L2207/06

摘要： A system, method, and apparatus for generating a low noise bias current to improve jitter performance in a wide frequency range LC-based phase-locked loop (PLL) circuit for multi-speed clocking applications. A plurality of noise-reducing stages are coupled in series and disposed between a power supply and a voltage controlled oscillator (VCO) including: a first stage VCO regulator; and a second stage bias circuit having a plurality of PMOS transistors cascode-coupled to each other and optionally grouped into one or more parallel branches of cascode-coupled transistor pairs. Each branch can be automatically enabled by a calibration code based on the desired reference clock signal in order to provide a wide range of currents to the voltage controlled oscillator. The cascode coupled pair includes a bias transistor coupled in series with a self-biased current buffer to provide high output impedance with minimal current change for any input voltage change from noise.

摘要翻译： 一种用于产生低噪声偏置电流以提高用于多速时钟应用的宽频率范围LC基锁相环（PLL）电路中的抖动性能的系统，方法和装置。 多个降噪级串联耦合并设置在电源和压控振荡器（VCO）之间，包括：第一级VCO调节器; 以及第二级偏置电路，其具有彼此串联耦合并可选地分组成共源共栅晶体管对的一个或多个并联支路的多个PMOS晶体管。 可以通过基于所需参考时钟信号的校准码来自动启用每个分支，以便向压控振荡器提供宽范围的电流。 共源共栅耦合对包括与自偏置电流缓冲器串联耦合的偏置晶体管，以便为噪声的任何输入电压变化提供最小电流变化的高输出阻抗。