公开(公告)号：US09214861B2

公开(公告)日：2015-12-15

申请号：US13930037

申请日：2013-06-28

Applicant: Chi-Ming Wang ,  Masaki Wasekura ,  Robert D. Lorenz

Inventor： Chi-Ming Wang ,  Masaki Wasekura ,  Robert D. Lorenz

IPC: H02M7/5387 ,  H02M3/156 ,  H02M1/00

CPC classification number: H02M3/156 ,  H02M2001/0025

Abstract: A DC-to-DC, converter that can reduce a loss of the converter is provided. The DC-to-DC converter includes an inductor, a switching transistor connected to the inductor, and a controller that drives the transistor. The controller acquires a next step reference value for the DC-to-DC converter in a sampling time Ta. The next step reference value is expressed by an output voltage of the DC-to-DC converter or a flux linkage of the inductor. The controller determines interpolating points between a current state value that corresponds to the current reference value and the next step reference value in a sampling time Ts that is shorter than the sampling time Ta based on a loss of the DC-to-DC converter while changing from the current state value to the next step reference value. The controller supplies to the switching transistor the PWM signals with a duty that corresponds to each of the interpolating points.

Abstract translation: 提供了可以减少转换器损耗的DC-DC转换器。 DC-DC转换器包括电感器，连接到电感器的开关晶体管和驱动晶体管的控制器。 控制器在采样时间Ta中获取DC-DC转换器的下一步参考值。 下一步参考值由DC-DC转换器的输出电压或电感器的磁链表示。 控制器基于DC-DC转换器的损耗，在改变时，基于DC-DC转换器的损耗，在比采样时间Ta短的采样时间Ts中，确定对应于当前参考值的当前状态值与下一个步进参考值之间的内插点 从当前状态值到下一步参考值。 控制器向开关晶体管提供具有对应于每个内插点的占空比的PWM信号。

公开(公告)号：US08169831B2

公开(公告)日：2012-05-01

申请号：US13100164

申请日：2011-05-03

Applicant: Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

Inventor： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/02 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

Abstract: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

Abstract translation: 提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。 预充电电路耦合到用于将节点充电到初始电压的节点。 中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。 电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。 这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

公开(公告)号：US20110205804A1

公开(公告)日：2011-08-25

申请号：US13100164

申请日：2011-05-03

Applicant: Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

Inventor： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

IPC: G11C16/28

CPC classification number: G11C16/26 ,  G11C7/02 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

Abstract: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

Abstract translation: 提供用于感测并联感测的一组非易失性存储器单元中的存储器单元的传导电流的感测电路，并将其结果提供给数据总线。 预充电电路耦合到用于将节点充电到初始电压的节点。 中间电路也耦合到节点并且可连接到存储器单元，由此来自预充电电路的电流可以被提供给存储单元。 电路还包括比较器电路，用于通过节点处的放电速率来确定传导电流; 耦合到所述比较器电路以保持所述确定的结果的数据锁存器; 以及传输门，其耦合到数据锁存器，以将保存在其中的结果独立于该节点提供给数据总线。 这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。

公开(公告)号：US07518910B2

公开(公告)日：2009-04-14

申请号：US11315817

申请日：2005-12-21

Applicant: Jian Chen ,  Chi-Ming Wang

Inventor： Jian Chen ,  Chi-Ming Wang

IPC: G11C11/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

Abstract translation: 根据各种实施例的系统和方法可以提供非易失性半导体存储器中减少的程序干扰。 在一个实施例中，使用与编程其他单元或字线的相应级别不同的一个或多个程序验证电平或电压对连接到NAND串的最后字线的选择存储器单元进行编程。 一个示例性实施例包括在编程在程序操作期间编程用于字符串的最后一个字线时，使用较低的阈值电压验证电平来选择物理状态。 另一个实施例包括将较低编程电压施加到最后字线的编程存储单元以选择物理状态。 在一些示例性实施方式中，建立读取使用较低验证电平编程的状态的附加读取电平。 在一个实施例中，当编程选择存储器单元或字线（诸如要为NAND串编程的最后字线）时，使用大于标称步长的第二编程电压步长。

公开(公告)号：US07489542B2

公开(公告)日：2009-02-10

申请号：US11770466

申请日：2007-06-28

Applicant: Jian Chen ,  Chi-Ming Wang

Inventor： Jian Chen ,  Chi-Ming Wang

IPC: G11C11/34

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations. A second program voltage step size that is larger than a nominal step size is used in one embodiment when programming select memory cells or word lines, such as the last word line to be programmed for a NAND string.

Abstract translation: 根据各种实施例的系统和方法可以提供非易失性半导体存储器中减少的程序干扰。 在一个实施例中，使用与编程其他单元或字线的相应级别不同的一个或多个程序验证电平或电压对连接到NAND串的最后字线的选择存储器单元进行编程。 一个示例性实施例包括在编程在程序操作期间编程用于字符串的最后一个字线时，使用较低的阈值电压验证电平来选择物理状态。 另一个实施例包括将较低编程电压施加到最后字线的编程存储单元以选择物理状态。 在一些示例性实施方式中，建立读取使用较低验证电平编程的状态的附加读取电平。 在一个实施例中，当编程选择存储器单元或字线（诸如要为NAND串编程的最后字线）时，使用大于标称步长的第二编程电压步长。

公开(公告)号：US07319630B2

公开(公告)日：2008-01-15

申请号：US11019990

申请日：2004-12-20

Applicant: Chi-Ming Wang ,  Kuo-Lung Chen ,  Shouchang Tsao

Inventor： Chi-Ming Wang ,  Kuo-Lung Chen ,  Shouchang Tsao

IPC: G11C7/00

CPC classification number: G11C16/12

Abstract: A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A current mirroring scheme limits current supplied to the latch. This reduces a difference of the two supplies, positive voltage, ground, or negative voltages, during data changes. The circuit provides smaller device sizes and fast speeds when data changes in the latch, while also providing lower power consumption. The technique provides greater benefits as the voltage difference between the two power supplies is greater.

Abstract translation: 在用于解码，编程，擦除和其他操作的非易失性存储器集成电路中使用限流锁存电路。 在一个实现中，在两个电源线之间并联连接有多个锁存器。 当前的镜像方案限制提供给锁存器的电流。 在数据更改期间，可以减少两个电源，正电压，接地或负电压的差异。 当锁存器中的数据变化时，该电路提供较小的器件尺寸和快速速度，同时还提供较低的功耗。 当两个电源之间的电压差较大时，该技术提供了更大的益处。

公开(公告)号：US5917474A

公开(公告)日：1999-06-29

申请号：US792038

申请日：1997-01-31

Applicant: Chi-Ming Wang

Inventor： Chi-Ming Wang

IPC: G06F3/033 ,  G09G5/08

CPC classification number: G06F3/03549

Abstract: The present invention relates to a trackball/actuator assembly for a portable computer that includes one or more free pivot-arm key plates disposed around a trackball module. According to one embodiment of the present invention, it includes a housing having a top surface and sidewalls extending downward from opposite ends of the top surface, a first keyplate protruding from the top surface between the sidewalls, a second keyplate protruding from the top surface between the sidewalls, and a trackball disposed between the keyplates. First and second pivot joints formed integral to the first and second sidewalls, respectively, form a first horizontal axis between the sidewalls that is offset from the first keyplate. The first keyplate is rotatably coupled to first and second pivot joints so that it pivots freely about the first horizontal axis. Third and fourth pivot joints formed integral to said first and second sidewalls, respectively, form a second horizontal axis between the sidewalls that is offset from the second keyplate. The second keyplate is rotatably coupled to third and fourth pivot joints so that it rotates freely about the second horizontal axis.

Abstract translation: 本发明涉及一种用于便携式计算机的轨迹球/致动器组件，其包括设置在轨迹球模块周围的一个或多个自由枢轴臂键盘。 根据本发明的一个实施例，其包括具有顶表面和从顶表面的相对端向下延伸的侧壁的壳体，从侧壁之间的顶表面突出的第一键板，从顶表面之间突出的第二键板， 侧壁和设置在键盘之间的轨迹球。 分别形成为与第一和第二侧壁成一体的第一和第二枢转接头形成在从第一键板偏移的侧壁之间的第一水平轴线。 第一键盘可旋转地联接到第一和第二枢转接头，使得其绕第一水平轴线自由地枢转。 分别形成为与所述第一和第二侧壁成一体的第三和第四枢轴接头形成在从第二键板偏移的侧壁之间的第二水平轴线。 第二键盘可旋转地联接到第三和第四枢转接头，使得其绕第二水平轴线自由旋转。

公开(公告)号：US08228729B2

公开(公告)日：2012-07-24

申请号：US13333494

申请日：2011-12-21

Applicant: Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-Ho Kim

Inventor： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-Ho Kim

IPC: G11C16/04 ,  G11C7/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

Abstract translation: 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US20120113716A1

公开(公告)日：2012-05-10

申请号：US13333494

申请日：2011-12-21

Applicant: Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

Inventor： Bo Liu ,  Yan Li ,  Alexander Kwok-Tung Mak ,  Chi-Ming Wang ,  Eugene Jinglun Tam ,  Kwang-ho Kim

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/34 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

Abstract translation: 描述用于在多状态非易失性存储器中读取和写入数据的技术。 数据以二进制格式写入存储器，读入存储器中的数据寄存器，并在寄存器内“折叠”，然后以多状态格式写入存储器。 在折叠操作中，来自单个字线的二进制数据被折叠为多状态格式，并且当以多状态形式重写时，被写入另一个字线的仅一部分。 还描述了数据“展开”的相应的读取技术。 还提出了允许这种“折叠”操作的寄存器结构。 一组实施例包括本地内部数据总线，其允许在不同读/写堆栈的寄存器之间的数据，其中内部总线可以在内部数据折叠处理中使用。

公开(公告)号：US07957197B2

公开(公告)日：2011-06-07

申请号：US12128535

申请日：2008-05-28

Applicant: Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

Inventor： Hao Thai Nguyen ,  Man Lung Mui ,  Seungpil Lee ,  Fanglin Zhang ,  Chi-Ming Wang

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C7/02 ,  G11C7/06 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5634

Abstract: Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result of the sensing to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, by which current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination of the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of this determination; and a transfer gate coupled to the data latch to supply a latched result to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.

Abstract translation: 提供了用于感测并联感测的一组非易失性存储器单元中的存储单元的传导电流的感测电路，并将该感测的结果提供给数据总线。 预充电电路耦合到用于将节点充电到初始电压的节点。 中间电路也耦合到节点并且可连接到存储器单元，来自预充电电路的电流可以被提供给存储单元。 该电路还包括比较器电路，用于通过节点处的放电速率来执行导通电流的确定; 耦合到所述比较器电路以保持所述确定结果的数据锁存器; 以及传输门，耦合到数据锁存器，以将锁存的结果提供给独立于该节点的数据总线。 这种布置提高了感测性能，并且可以帮助消除感测过程中模拟感测路径上的噪声并降低开关电流。