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    Method for end point detection of polysilicon chemical mechanical polishing in an anti-fuse memory device
    1.
    发明申请
    Method for end point detection of polysilicon chemical mechanical polishing in an anti-fuse memory device 有权
    反熔丝存储器件中多晶硅化学机械抛光的端点检测方法

    公开(公告)号：US20050170563A1

    公开(公告)日：2005-08-04

    申请号：US10767276

    申请日：2004-01-29

    申请人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    发明人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    IPC分类号： H01L21/461 ,  H01L21/768 ,  H01L21/82 ,  H01L27/10

    CPC分类号： H01L21/7684 ,  H01L21/76819 ,  H01L27/10

    摘要： A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

    摘要翻译： 实现了在制造集成电路器件时抛光导线的新方法。 该方法包括提供覆盖在衬底上的多条导线。 将高密度等离子体（HDP）氧化物层沉积在衬底和导电线上。 在导电线之间的区域中，HDP氧化物层的第一平坦表面形成在导线的顶部下方。 将HDP氧化物层溅射到覆盖导电线上，使得HDP氧化物层的第二平面形成在导电线之上。 抛光停止层沉积在HDP氧化物层上。 沉积在抛光停止层上的膜层。 将薄膜层抛光到覆盖第二平面顶表面的抛光停止层。 将薄膜层，抛光阻止层和导电线抛光到覆盖第一平面顶表面的抛光停止层，以完成导线的抛光。

    Nonvolatile semiconductor memory device
    3.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US07608926B2

    公开(公告)日：2009-10-27

    申请号：US11326904

    申请日：2006-01-06

    申请人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    发明人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    IPC分类号： H01L23/48 ,  H01L23/52

    CPC分类号： H01L21/7684 ,  H01L21/76819 ,  H01L27/10

    摘要： A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

    摘要翻译： 实现了在制造集成电路器件时抛光导线的新方法。 该方法包括提供覆盖在衬底上的多条导线。 将高密度等离子体（HDP）氧化物层沉积在衬底和导电线上。 在导电线之间的区域中，HDP氧化物层的第一平坦表面形成在导线的顶部下方。 将HDP氧化物层溅射到覆盖导电线上，使得HDP氧化物层的第二平面形成在导电线之上。 抛光停止层沉积在HDP氧化物层上。 沉积在抛光停止层上的膜层。 将薄膜层抛光至覆盖第二平面顶表面的抛光停止层。 将薄膜层，抛光阻止层和导电线抛光到覆盖第一平面顶表面的抛光停止层，以完成导线的抛光。

    Fabrication of stacked dielectric layer for suppressing electrostatic charge buildup
    4.
    发明授权
    Fabrication of stacked dielectric layer for suppressing electrostatic charge buildup 有权
    用于抑制静电电荷积累的叠层电介质层的制造

    公开(公告)号：US07205209B2

    公开(公告)日：2007-04-17

    申请号：US10842971

    申请日：2004-05-11

    申请人： Chai-Tak Teh ,  Min-Nin Yu ,  Gary Yang ,  Han-Chung Chen ,  Yuan-Shin Jing ,  Jian-Liang Lin ,  Jui-Feng Jao

    发明人： Chai-Tak Teh ,  Min-Nin Yu ,  Gary Yang ,  Han-Chung Chen ,  Yuan-Shin Jing ,  Jian-Liang Lin ,  Jui-Feng Jao

    IPC分类号： H01L21/331

    CPC分类号： H01L21/02304 ,  H01L21/02131 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/31629 ,  H01L21/76826 ,  H01L21/76834 ,  H01L21/76837

    摘要： A method of fabricating a stacked dielectric layer for suppressing electrostatic charge buildup. First, a substrate having metal layers thereon is provided, with a plurality of gaps formed therebetween. Next, a dielectric layer is formed by simultaneous deposition and ion-bombardment, such that the dielectric layer covers the bottom dielectric liner and fills the gaps. Finally, a top dielectric liner is formed on the dielectric layer by deposition without ion-bombardment. Furthermore, the present invention provides another method to fabricate a stacked dielectric layer by performing a plasma treatment on the dielectric layer to suppress electrostatic charge buildup. As a result, the above-mentioned methods can efficiently avoid metal extrusion issues.

    摘要翻译： 一种制造用于抑制静电电荷累积的叠层电介质层的方法。 首先，提供其上具有金属层的基板，其间形成有多个间隙。 接下来，通过同时沉积和离子轰击形成电介质层，使得电介质层覆盖底部电介质衬垫并填充间隙。 最后，通过在没有离子轰击的情况下进行沉积，在电介质层上形成顶部绝缘衬垫。 此外，本发明提供了通过在电介质层上进行等离子体处理以抑制静电电荷累积来制造叠层电介质层的另一种方法。 结果，上述方法可以有效地避免金属挤压问题。

    Nonvolatile semiconductor memory device
    5.
    发明申请
    Nonvolatile semiconductor memory device 有权

    公开(公告)号：US20060186546A1

    公开(公告)日：2006-08-24

    申请号：US11326904

    申请日：2006-01-06

    申请人： Kern Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    发明人： Kern Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    IPC分类号： H01L23/52

    CPC分类号： H01L21/7684 ,  H01L21/76819 ,  H01L27/10

    摘要： A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

    Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device
    6.
    发明授权
    Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device 有权
    用于端点检测的方法多晶硅化学机械抛光在反熔丝存储器件中

    公开(公告)号：US07012021B2

    公开(公告)日：2006-03-14

    申请号：US10767276

    申请日：2004-01-29

    申请人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    发明人： Kern-Huat Ang ,  Chai-Chen Liu ,  Chiang-Yung Ku ,  Jui-Feng Jao ,  Sheng-Chen Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  H01L21/76819 ,  H01L27/10

    摘要： A new method to polish down conductive lines in the manufacture of an integrated circuit device is achieved. The method comprises providing a plurality of conductive lines overlying a substrate. A high density plasma (HDP) oxide layer is deposited overlying the substrate and the conductive lines. In the regions between the conductive lines, first planar surfaces of the HDP oxide layer are formed below the top of the conductive lines. The HDP oxide layer is sputtered down overlying the conductive lines such that second planar surfaces of the HDP oxide layer are formed above the conductive lines. A polish stopping layer is deposited overlying the HDP oxide layer. A film layer is deposited overlying the polish stopping layer. The film layer is polished down to the polish stopping layer overlying the second planar top surfaces. The film layer, the polish stopping layer, and the conductive lines are polished down to the polish stopping layer overlying the first planar top surfaces to complete the polishing down of the conductive lines.

    摘要翻译： 实现了在制造集成电路器件时抛光导线的新方法。 该方法包括提供覆盖在衬底上的多条导线。 将高密度等离子体（HDP）氧化物层沉积在衬底和导电线上。 在导电线之间的区域中，HDP氧化物层的第一平坦表面形成在导线的顶部下方。 将HDP氧化物层溅射到覆盖导电线上，使得HDP氧化物层的第二平面形成在导电线之上。 抛光停止层沉积在HDP氧化物层上。 沉积在抛光停止层上的膜层。 将薄膜层抛光至覆盖第二平面顶表面的抛光停止层。 将薄膜层，抛光阻止层和导电线抛光到覆盖第一平面顶表面的抛光停止层，以完成导线的抛光。