公开(公告)号：US09213631B2

公开(公告)日：2015-12-15

申请号：US13555206

申请日：2012-07-23

申请人： Chien-Hua Chu

发明人： Chien-Hua Chu

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F12/0238 ,  G06F2212/7201

摘要： A data processing method for a re-writable non-volatile memory module is provided. The method includes receiving a write data stream associating to a logical access address of a logical programming unit; selecting a physical programming unit; and determining whether the write data stream associates with a kind of pattern. The method includes, if the write data stream associates with the kind of pattern, setting identification information corresponding to the logical access address as an identification value corresponding to the pattern, and storing the identification information corresponding to the logical access address into a predetermined area, wherein the write data stream is not programmed into the selected physical programming unit. The method further includes mapping the logical programming unit to the physical programming unit. Accordingly, the method can effectively shorten the time for writing data into the re-writable non-volatile memory module.

摘要翻译： 提供了一种用于可重写非易失性存储器模块的数据处理方法。 该方法包括接收与逻辑编程单元的逻辑访问地址相关联的写入数据流; 选择物理编程单元; 以及确定写入数据流是否与一种模式相关联。 该方法包括：如果写入数据流与图案的种类相关联，则将与逻辑访问地址相对应的识别信息设置为与该模式对应的识别值，并将对应于逻辑访问地址的识别信息存储到预定区域中， 其中写入数据流不被编程到所选择的物理编程单元中。 该方法还包括将逻辑编程单元映射到物理编程单元。 因此，该方法可以有效地缩短将数据写入可重写的非易失性存储器模块的时间。

公开(公告)号：US08706948B2

公开(公告)日：2014-04-22

申请号：US13477813

申请日：2012-05-22

申请人： Chien-Hua Chu ,  Hong-Lipp Ko

发明人： Chien-Hua Chu ,  Hong-Lipp Ko

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F3/06

CPC分类号： G06F3/0601 ,  G06F1/3203 ,  G06F1/3275 ,  G06F13/1684 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface.

摘要翻译： 提供一种用于将数据从主机系统写入可重写非易失性存储装置的多个存储器管芯中的数据写入方法。 数据写入方法包括确定主机系统的数据传输接口是否符合第一接口标准或第二接口标准。 数据写入方法还包括当主机系统的数据传输接口符合第一接口标准并使用省电模式将数据写入存储器管芯时将数据写入存储器管芯，当数据 主机系统的传输接口符合第二接口标准。 因此，数据写入方法可以有效地防止可重写非易失性存储装置的稳定性由于数据传输接口所提供的功率不足而降低。

公开(公告)号：US20140071585A1

公开(公告)日：2014-03-13

申请号：US13609739

申请日：2012-09-11

申请人： Pin-Yuan Yu ,  Yi-Chun Shao ,  Chien-Hua Chu

发明人： Pin-Yuan Yu ,  Yi-Chun Shao ,  Chien-Hua Chu

IPC分类号： H01G4/005

CPC分类号： H01G4/005 ,  H01G4/33 ,  H01L28/92

摘要： A vertical semiconductor charge storage structure includes a substrate, at least one lower electrode, a dielectric layer and an upper electrode. The lower electrode includes a lower conductor, and a first side conductor and a second side conductor connected to the lower conductor. The first side conductor and the second side conductor are parallel to each other and form an included angle with the lower conductor. A height of the first side conductor from the substrate is greater than a height of the second side conductor from the substrate. The dielectric layer and the upper electrode are sequentially formed on surfaces of the substrate and the lower electrode. Accordingly, by forming the first side conductor and the second side conductor at different heights, an aperture ratio is increased to reduce difficulty in filling or deposition in subsequent processes to further enhance an overall yield rate.

摘要翻译： 垂直半导体电荷存储结构包括衬底，至少一个下电极，电介质层和上电极。 下电极包括下导体和连接到下导体的第一侧导体和第二侧导体。 第一侧导体和第二侧导体彼此平行并与下导体形成夹角。 第一侧导体与衬底的高度大于第二侧导体与衬底的高度。 电介质层和上电极依次形成在基板和下电极的表面上。 因此，通过以不同的高度形成第一侧导体和第二侧导体，增加开口率以减少后续处理中的填充或沉积的困难，以进一步提高总的屈服率。

公开(公告)号：US20130332791A1

公开(公告)日：2013-12-12

申请号：US13591236

申请日：2012-08-22

申请人： Chien-Hua Chu

发明人： Chien-Hua Chu

IPC分类号： G06F11/08 ,  G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/403 ,  G06F2212/7211 ,  G11C2211/5641

摘要： A data protection method adapted to a rewritable non-volatile memory module having a plurality of physical blocks is provided. The data protection method includes following steps. If the rewritable non-volatile memory module is powered on, a power-off period from last time the rewritable non-volatile memory module is powered off till present is obtained. If the power-off period is longer than a time threshold, whether each physical block satisfies an update condition is determined according to a block information of the physical block. An update procedure is executed on the physical blocks that satisfy the update condition. The update procedure is configured to read data from a physical block and rewrite the data into one of the physical blocks. Thereby, data in the physical blocks is protected from being easily lost, and the lifespan of the rewritable non-volatile memory module is prolonged.

摘要翻译： 提供了一种适用于具有多个物理块的可重写非易失性存储器模块的数据保护方法。 数据保护方法包括以下步骤。 如果可重写非易失性存储器模块通电，则可以从上一次断开可重写非易失性存储器模块断电直到存在。 如果断电时间长于时间阈值，则根据物理块的块信息确定每个物理块是否满足更新条件。 对满足更新条件的物理块执行更新过程。 更新过程被配置为从物理块读取数据并将数据重写为物理块之一。 从而保护物理块中的数据免于容易丢失，并且延长了可重写非易失性存储器模块的寿命。

公开(公告)号：US20130275654A1

公开(公告)日：2013-10-17

申请号：US13548169

申请日：2012-07-12

申请人： Chien-Hua Chu

发明人： Chien-Hua Chu

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F1/3275 ,  G06F2212/1028 ,  G06F2212/7203 ,  Y02D10/13 ,  Y02D10/14

摘要： A memory storage apparatus having a rewritable non-volatile memory module, a first circuit, a memory controller and a power management circuit is provided. The first circuit outputs a state signal and keeps the state signal in a first state when the first circuit is enabled, and then the first circuit keeps the state signal in a second state after a predetermined condition is satisfied. When the memory controller receives a first signal, the power management circuit stops supplying an output voltage to the rewritable non-volatile memory module and the memory controller. Additionally, when the memory controller is enabled, the memory controller determines whether the state signal is in the first state. If true, the memory controller performs a first procedure; and if not, the memory controller performs a second procedure.

摘要翻译： 提供具有可重写非易失性存储器模块，第一电路，存储器控制器和电源管理电路的存储器存储装置。 当第一电路被使能时，第一电路输出状态信号并将状态信号保持在第一状态，然后在满足预定条件之后，第一电路将状态信号保持在第二状态。 当存储器控制器接收到第一信号时，电源管理电路停止向可重写非易失性存储器模块和存储器控制器提供输出电压。 此外，当存储器控制器被使能时，存储器控制器确定状态信号是否处于第一状态。 如果为真，则存储器控制器执行第一过程; 如果不是，则存储器控制器执行第二过程。

公开(公告)号：US20130237073A1

公开(公告)日：2013-09-12

申请号：US13556362

申请日：2012-07-24

申请人： CHIA-TSANG HSU ,  CHIEN-HUA CHU

发明人： CHIA-TSANG HSU ,  CHIEN-HUA CHU

IPC分类号： H01R13/44

CPC分类号： H01R31/065 ,  H01R13/71

摘要： A rotatable plug includes a casing unit having a first casing part and a second casing part with a pair of receiving spaces, a pair of conductive terminals respectively having conductive sections, and a rotatable unit including a pivot shaft, a pair of conductive prongs connected transversely to the pivot shaft, and a pair of conductive protrusions protruding out from the pivot shaft. The rotatable unit is rotatable relative to the casing unit between non-use and use positions, where the conductive prongs are accommodated in and extend out of the receiving spaces, respectively. Each conductive protrusion has at least two points of contact with the conductive section of a respective conductive terminal.

摘要翻译： 可旋转插头包括壳体单元，该壳体单元具有第一壳体部分和具有一对接收空间的第二壳体部分，分别具有导电部分的一对导电端子和包括枢轴的可旋转单元，横向连接的一对导电插脚 枢转轴，以及从枢轴突出的一对导电突起。 可旋转单元可相对于壳体单元在非使用位置和使用位置之间转动，其中导电插脚分别容纳在接收空间中并从接收空间延伸出。 每个导电突起与相应导电端子的导电部分具有至少两个接触点。

公开(公告)号：US20130080680A1

公开(公告)日：2013-03-28

申请号：US13297280

申请日：2011-11-16

申请人： Chien-Hua Chu

发明人： Chien-Hua Chu

IPC分类号： G06F12/00 ,  G06F12/06

CPC分类号： G11C7/04 ,  G06F12/0246 ,  G11C11/40615

摘要： A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and a memory controller used for controlling the rewritable non-volatile memory module are provided. The temperature management method includes detecting and determining whether the hot-spot temperature of the memory storage device is higher than a predetermined temperature; and when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the memory storage device. Accordingly, the problem of heat buildup of the (rewritable non-volatile) memory storage device can be mitigated, as well as the problems of data loss and device aging of the (rewritable non-volatile) memory storage device.

摘要翻译： 提供一种适用于具有可重写非易失性存储器模块和用于控制可重写非易失性存储器模块的存储器控​​制器的存储器存储装置的温度管理方法。 温度管理方法包括检测和确定存储器存储装置的热点温度是否高于预定温度; 并且当肯定时，使存储器控制器执行冷却处理，以便降低存储器存储装置的热点温度。 因此，可以减轻（可重写非易失性）存储器件的积聚问题，以及（可重写非易失性）存储器件的数据丢失和器件老化的问题。

公开(公告)号：US08386905B2

公开(公告)日：2013-02-26

申请号：US12785729

申请日：2010-05-24

申请人： Chien-Hua Chu

发明人： Chien-Hua Chu

IPC分类号： G06F11/00

CPC分类号： G06F11/1048 ,  H03M13/05

摘要： An error correcting method for a memory chip is provided. The memory chip has a plurality of physical blocks, each of the physical blocks has a plurality of physical pages, and the physical pages belonging to the same physical block are individually written and simultaneously erased. The error correcting method includes sequentially writing a plurality of data into the physical pages of a first physical block and generating a parity information according to the data. The error correcting method further includes writing the parity information into one of the physical pages of the first physical block following the data and correcting the data in the first physical block according to the parity information. Accordingly, the parity information can be used for correcting error bits in the data when an error checking and correcting circuit can not correct the error bits. Thereby, the error correcting ability is enhanced.

摘要翻译： 提供了一种用于存储芯片的纠错方法。 存储器芯片具有多个物理块，每个物理块具有多个物理页，并且属于同一物理块的物理页被单独写入并同时擦除。 误差校正方法包括：将多个数据顺序地写入第一物理块的物理页面，并根据该数据生成奇偶校验信息。 错误校正方法还包括将奇偶校验信息写入数据之后的第一物理块的物理页之一，并根据奇偶校验信息对第一物理块中的数据进行校正。 因此，当错误检查和校正电路不能校正错误位时，奇偶信息可以用于校正数据中的错误位。 由此，提高了纠错能力。

公开(公告)号：US08266334B2

公开(公告)日：2012-09-11

申请号：US12764583

申请日：2010-04-21

申请人： Chien-Hua Chu ,  Hong-Lipp Ko

发明人： Chien-Hua Chu ,  Hong-Lipp Ko

IPC分类号： G06F3/00 ,  G06F1/00

CPC分类号： G06F3/0601 ,  G06F1/3203 ,  G06F1/3275 ,  G06F13/1684 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： A data writing method for writing data from a host system into a plurality of memory dies of a rewritable non-volatile memory storage apparatus is provided. The data writing method includes determining whether the data transmission interface of the host system complies with a first interface standard or a second interface standard. The data writing method also includes using a general mode to write the data into the memory dies when the data transmission interface of the host system complies with the first interface standard and using a power saving mode to write the data into the memory dies when the data transmission interface of the host system complies with the second interface standard. Accordingly, the data writing method can effectively prevent the stability of the rewritable non-volatile memory storage apparatus from reducing due to insufficient power supplied by the data transmission interface.

摘要翻译： 提供一种用于将数据从主机系统写入可重写非易失性存储装置的多个存储器管芯中的数据写入方法。 数据写入方法包括确定主机系统的数据传输接口是否符合第一接口标准或第二接口标准。 数据写入方法还包括当主机系统的数据传输接口符合第一接口标准并使用省电模式将数据写入存储器管芯时将数据写入存储器管芯，当数据 主机系统的传输接口符合第二接口标准。 因此，数据写入方法可以有效地防止可重写非易失性存储装置的稳定性由于数据传输接口所提供的功率不足而降低。

公开(公告)号：US08225067B2

公开(公告)日：2012-07-17

申请号：US12413071

申请日：2009-03-27

申请人： Chien-Hua Chu ,  Chih-Kang Yeh ,  Kok-Yong Tan

发明人： Chien-Hua Chu ,  Chih-Kang Yeh ,  Kok-Yong Tan

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7202 ,  G11C11/5628 ,  G11C29/82

摘要： A multi level cell (MLC) NAND flash memory storage system is provided. A controller of the MLC NAND flash memory storage system declares it a signal level cell (SLC) NAND flash memory chip to a host system connected thereto and provides a plurality of SLC logical blocks to the host system. When the controller receives a write command and a user data from the host system, the controller writes the user data into a page of a MLC physical block and records the page of the SLC logical block corresponding to the page of the MLC physical block. When the controller receives an erase command from the host system, the controller writes a predetermined data into the page of the MLC physical block mapped to the SLC logical block to be erased, wherein the predetermined data has the same pattern as a pattern of the erased page.

摘要翻译： 提供了多级单元（MLC）NAND闪存存储系统。 MLC NAND闪存存储系统的控制器将信号级单元（SLC）NAND闪速存储器芯片声明到连接到其的主机系统，并向主机系统提供多个SLC逻辑块。 当控制器从主机系统接收写入命令和用户数据时，控制器将用户数据写入MLC物理块的页面，并记录与MLC物理块的页面相对应的SLC逻辑块的页面。 当控制器从主机系统接收到擦除命令时，控制器将预定数据写入映射到要擦除的SLC逻辑块的MLC物理块的页面，其中预定数据具有与擦除的模式相同的模式 页。