公开(公告)号：US20100270599A1

公开(公告)日：2010-10-28

申请号：US12542214

申请日：2009-08-17

申请人： CHIH-CHIANG KUO ,  CHIN-LIEN LIN

发明人： CHIH-CHIANG KUO ,  CHIN-LIEN LIN

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28211 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/78

摘要： A transistor structure with high reliability includes a substrate unit, a solid ozone boundary layer, a gate oxide layer and a gate electrode. In addition, the substrate unit has a substrate body, a source electrode exposed on a top surface of the substrate body, and a drain electrode exposed on the top surface of the substrate body and separated from the source electrode by a predetermined distance. The solid ozone boundary layer is gradually grown on the top surface of the substrate body by continually mixing gaseous ozone into deionized water under 40˜95□, and the solid ozone boundary layer is formed between the source electrode and the drain electrode and formed on the substrate body. The gate oxide layer is formed on a top surface of the solid ozone boundary layer. The gate electrode is formed on a top surface of the gate oxide layer.

摘要翻译： 具有高可靠性的晶体管结构包括基板单元，固体臭氧边界层，栅极氧化物层和栅电极。 此外，基板单元具有基板主体，暴露在基板主体的上表面上的源电极和暴露在基板主体的顶表面上并与源电极隔开预定距离的漏电极。 固体臭氧边界层通过将气态臭氧连续地混合到40〜95℃的去离子水中而逐渐生长在基体的顶表面上，固体臭氧边界层形成在源电极和漏电极之间，形成在 基体。 栅氧化层形成在固体臭氧边界层的顶表面上。 栅电极形成在栅极氧化物层的顶表面上。

公开(公告)号：US20080261364A1

公开(公告)日：2008-10-23

申请号：US11738511

申请日：2007-04-22

申请人： Shian-Hau Liao ,  Tsung-Shin Wu ,  Chih-Chiang Kuo ,  Chien-Li Cheng

发明人： Shian-Hau Liao ,  Tsung-Shin Wu ,  Chih-Chiang Kuo ,  Chien-Li Cheng

IPC分类号： H01L29/00

CPC分类号： H01L28/91

摘要： A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to form a tapered trench in the bottom layer, the BPSG layer and the USG layer; removing the top layer to perform a selective wet etching process to partially remove the BPSG layer; depositing conformally a poly-Si layer and filling the trench with a sacrificial layer; removing the poly-Si layer unmasked by the sacrificial layer; using the bottom layer as a second etching stop layer to perform a wet etching process to remove the USG layer and BPSG layer; performing a static drying process; and depositing a dielectric layer and a conductive material to form the stack capacitor.

摘要翻译： 形成堆叠电容器的方法包括在其上提供具有底层，BPSG层，USG层和顶层的衬底; 使用顶层作为硬掩模，并且将基板作为第一蚀刻停止层，以执行干蚀刻工艺以在底层，BPSG层和USG层中形成锥形沟槽; 去除顶层以执行选择性湿蚀刻工艺以部分去除BPSG层; 沉积多晶硅层并用牺牲层填充沟槽; 去除由牺牲层未掩蔽的多晶硅层; 使用底层作为第二蚀刻停止层进行湿蚀刻工艺以去除USG层和BPSG层; 进行静态干燥过程; 以及沉积介质层和导电材料以形成堆叠电容器。

公开(公告)号：US07473598B2

公开(公告)日：2009-01-06

申请号：US11738511

申请日：2007-04-22

申请人： Shian-Hau Liao ,  Tsung-Shin Wu ,  Chih-Chiang Kuo ,  Chien-Li Cheng

发明人： Shian-Hau Liao ,  Tsung-Shin Wu ,  Chih-Chiang Kuo ,  Chien-Li Cheng

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L21/4763

CPC分类号： H01L28/91

摘要： A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to form a tapered trench in the bottom layer, the BPSG layer and the USG layer; removing the top layer to perform a selective wet etching process to partially remove the BPSG layer; depositing conformally a poly-Si layer and filling the trench with a sacrificial layer; removing the poly-Si layer unmasked by the sacrificial layer; using the bottom layer as a second etching stop layer to perform a wet etching process to remove the USG layer and BPSG layer; performing a static drying process; and depositing a dielectric layer and a conductive material to form the stack capacitor.

摘要翻译： 形成堆叠电容器的方法包括在其上提供具有底层，BPSG层，USG层和顶层的衬底; 使用顶层作为硬掩模，并且将基板作为第一蚀刻停止层，以执行干蚀刻工艺以在底层，BPSG层和USG层中形成锥形沟槽; 去除顶层以执行选择性湿蚀刻工艺以部分去除BPSG层; 沉积多晶硅层并用牺牲层填充沟槽; 去除由牺牲层未掩蔽的多晶硅层; 使用底层作为第二蚀刻停止层进行湿蚀刻工艺以去除USG层和BPSG层; 进行静态干燥过程; 以及沉积介质层和导电材料以形成堆叠电容器。

公开(公告)号：US20110230236A1

公开(公告)日：2011-09-22

申请号：US13051080

申请日：2011-03-18

申请人： Chung-Yung Tsai ,  Wei-Hsiang Wang ,  Chih-Chiang Kuo

发明人： Chung-Yung Tsai ,  Wei-Hsiang Wang ,  Chih-Chiang Kuo

IPC分类号： H04B1/38

CPC分类号： H04L12/2818 ,  H04L12/2825 ,  H04L2012/2841

摘要： The present invention discloses an integrated system for remote monitoring home appliances by a cell phone. In the integrated system, a cell phone sends an instruction message to a computer by a wireless network. A digital control disk connected with the computer generates a control signal in accordance with the instruction message. The control signal is sent by a wireless transceiver circuit to a home appliance. Moreover, a state signal that includes information of the home appliance operation can be sent to the digital control disk. Through the computer connecting to the wireless network, the cell phone is informed of the information of the home appliance operation. Thereby, the user can control the home appliances and acquire the current operation states of the home appliances by his/her cell phone.

摘要翻译： 本发明公开了一种通过手机远程监控家用电器的集成系统。 在集成系统中，手机通过无线网络向计算机发送指令消息。 与计算机连接的数字控制盘根据指令消息生成控制信号。 控制信号由无线收发器电路发送到家用电器。 此外，包括家用电器操作的信息的状态信号可以被发送到数字控制盘。 通过连接到无线网络的计算机，向手机通知家电操作的信息。 因此，用户可以通过他/她的手机控制家用电器并获取家用电器的当前操作状态。

公开(公告)号：US20090311842A1

公开(公告)日：2009-12-17

申请号：US12197321

申请日：2008-08-25

申请人： Chih-Chiang Kuo

发明人： Chih-Chiang Kuo

IPC分类号： H01L21/02

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： A method for fabricating a semiconductor memory device includes providing a substrate having thereon a conductive layer, forming an etching stop layer, a first dielectric layer and a second dielectric layer on the substrate, etching high aspect ratio hole into the etching stop layer, the first dielectric layer and the second dielectric layer to expose a portion of the conductive layer, thereafter selectively removing the first dielectric layer from the hole, thereby forming a bottle-shaped hole, then forming a conductive layer on interior surface of the bottle-shaped hole, and then stripping the first and second dielectric layers.

摘要翻译： 一种半导体存储器件的制造方法，其特征在于，在基板上设置有具有导电层的基板，形成蚀刻停止层，第一电介质层和第二电介质层，将蚀刻停止层的高纵横比孔蚀刻， 电介质层和第二电介质层，以暴露导电层的一部分，然后从孔中选择性地除去第一介电层，从而形成瓶形孔，然后在瓶形孔的内表面上形成导电层， 然后剥离第一和第二介电层。