公开(公告)号：US20080211545A1

公开(公告)日：2008-09-04

申请号：US11744225

申请日：2007-05-04

Applicant: Chih-Jen Yen ,  Chih-Yuan Hsieh ,  Chiu-Hung Cheng

Inventor： Chih-Jen Yen ,  Chih-Yuan Hsieh ,  Chiu-Hung Cheng

IPC: G11C27/02

CPC classification number: G11C27/026

Abstract: A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively.

Abstract translation: 提供了采样保持装置及其操作方法。 采样保持装置包括采样放大器，晶体管，第一开关，第二开关，采样电容器和漏极充电单元。 采样放大器的第一输入端接收输入信号。 晶体管的第一端耦合到第一电压。 第一开关耦合在采样放大器的输出端和晶体管的栅极之间。 第二开关的第一和第二端子分别耦合到晶体管的第二端子和采样放大器的第二输入端子。 采样电容器的第一和第二端子耦合到晶体管的栅极和参考电压。 用于排放/提供电荷的漏极 - 充电单元分别具有耦合到第二开关的第二端子的第一和第二端子以及第二电压。

公开(公告)号：US20070120610A1

公开(公告)日：2007-05-31

申请号：US11307882

申请日：2006-02-27

Applicant: Chiu-Hung Cheng ,  Chih-Jen Yen

Inventor： Chiu-Hung Cheng ,  Chih-Jen Yen

IPC: H03L7/00

CPC classification number: H03L7/0898 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A method for reducing phase lock time and jittering and a phase lock loop (PLL) using the same adapted for PLL including a charge pump (CP) which includes a pull-up and a pull-down networks used for controlling output voltage of the CP. The output voltage is used for controlling frequency and phase of an output signal of the PLL. The method includes: receiving a reference and a feedback signals; setting the driving capabilities of the pull-up and the pull-down networks to a first driving capability when the phase difference between the reference and the feedback signals is greater than a predetermined value; setting the driving capabilities of the pull-up and the pull-down networks to a second driving capability when the phase difference between the reference and the feedback signals is smaller than the predetermined value, wherein the first driving capability is greater than the second driving capability.

Abstract translation: 一种减少相位锁定时间和抖动的方法以及使用适用于PLL的相位锁相环（PLL）的方法，该PLL包括一个电荷泵（CP），该电荷泵（CP）包括用于控制CP的输出电压的上拉和下拉网络 。 输出电压用于控制PLL输出信号的频率和相位。 该方法包括：接收参考和反馈信号; 当参考和反馈信号之间的相位差大于预定值时，将上拉和下拉网络的驱动能力设置为第一驱动能力; 当基准和反馈信号之间的相位差小于预定值时，将上拉和下拉网络的驱动能力设定为第二驱动能力，其中第一驱动能力大于第二驱动能力 。

公开(公告)号：US20070018734A1

公开(公告)日：2007-01-25

申请号：US11163122

申请日：2005-10-05

Applicant: Chiu-Hung Cheng ,  Chih-Jen Yen

Inventor： Chiu-Hung Cheng ,  Chih-Jen Yen

IPC: H03L7/00

CPC classification number: H03L7/0891 ,  H03L7/14 ,  H03L7/18

Abstract: A method and an apparatus for stabilizing output from a Phase Lock Loop (PLL) and the PLL thereof is disclosed. The method mainly relates to enabling the control voltage of a voltage control oscillator VCO in the PLL remained unchanged by means of turning off a charge-discharge current source of a charge pump in a PLL in response to a detected reference signal lower than a default value. Furthermore, the method enables the pulse frequency output from the VCO no exceeding a default tolerant frequency range in a distance from a desired output frequency. Thus, when the reference signal resumes the original frequency, the PLL can quickly lock the phase and the frequency again.

Abstract translation: 公开了一种用于稳定锁相环（PLL）的输出及其PLL的方法和装置。 该方法主要涉及通过响应于低于默认值的检测到的参考信号，通过关闭PLL中的电荷泵的充电 - 放电电流源来使PLL中的压控振荡器VCO的控制电压保持不变 。 此外，该方法使得来自VCO的脉冲频率输出不会超过与期望的输出频率相距一定距离的默认容限频率范围。 因此，当参考信号恢复原始频率时，PLL可以再次快速锁定相位和频率。

公开(公告)号：US07605663B2

公开(公告)日：2009-10-20

申请号：US11163122

申请日：2005-10-05

Applicant: Chiu-Hung Cheng ,  Chih-Jen Yen

Inventor： Chiu-Hung Cheng ,  Chih-Jen Yen

IPC: H03L7/08

CPC classification number: H03L7/0891 ,  H03L7/14 ,  H03L7/18

Abstract: A method and an apparatus for stabilizing output from a Phase Lock Loop (PLL) and the PLL thereof is disclosed. The method mainly relates to enabling the control voltage of a voltage control oscillator VCO in the PLL remained unchanged by means of turning off a charge-discharge current source of a charge pump in a PLL in response to a detected reference signal lower than a default value. Furthermore, the method enables the pulse frequency output from the VCO no exceeding a default tolerant frequency range in a distance from a desired output frequency. Thus, when the reference signal resumes the original frequency, the PLL can quickly lock the phase and the frequency again.

Abstract translation: 公开了一种用于稳定锁相环（PLL）的输出及其PLL的方法和装置。 该方法主要涉及通过响应于低于默认值的检测到的参考信号，通过关闭PLL中的电荷泵的充电 - 放电电流源来使PLL中的压控振荡器VCO的控制电压保持不变 。 此外，该方法使得来自VCO的脉冲频率输出不会超过与期望的输出频率相距一定距离的默认容限频率范围。 因此，当参考信号恢复原始频率时，PLL可以再次快速锁定相位和频率。

公开(公告)号：US07541846B2

公开(公告)日：2009-06-02

申请号：US11744225

申请日：2007-05-04

Applicant: Chih-Jen Yen ,  Chih-Yuan Hsieh ,  Chiu-Hung Cheng

Inventor： Chih-Jen Yen ,  Chih-Yuan Hsieh ,  Chiu-Hung Cheng

IPC: G11C27/02 ,  H03K17/00

CPC classification number: G11C27/026

Abstract: A sample-and-hold apparatus and an operating method thereof are provided. The sample-and-hold apparatus includes a sampling amplifier, a transistor, a first switch, a second switch, a sampling capacitor, and a drain-charge unit. A first input terminal of the sampling amplifier receives an input signal. A first-terminal of the transistor is coupled to a first voltage. The first switch is coupled between an output terminal of the sampling amplifier and a gate of the transistor. The first and second terminals of the second switch are coupled to a second terminal of the transistor and a second input terminal of the sampling amplifier, respectively. The first and second terminals of the sampling capacitor are coupled to the gate of the transistor and a reference voltage. The drain-charge unit for draining/providing charges has first and second terminals coupled to the second terminal of the second switch and a second voltage, respectively.

Abstract translation: 提供了采样保持装置及其操作方法。 采样保持装置包括采样放大器，晶体管，第一开关，第二开关，采样电容器和漏极充电单元。 采样放大器的第一输入端接收输入信号。 晶体管的第一端耦合到第一电压。 第一开关耦合在采样放大器的输出端和晶体管的栅极之间。 第二开关的第一和第二端子分别耦合到晶体管的第二端子和采样放大器的第二输入端子。 采样电容器的第一和第二端子耦合到晶体管的栅极和参考电压。 用于排放/提供电荷的漏极 - 充电单元分别具有耦合到第二开关的第二端子的第一和第二端子以及第二电压。

公开(公告)号：US07355487B2

公开(公告)日：2008-04-08

申请号：US11307882

申请日：2006-02-27

Applicant: Chiu-Hung Cheng ,  Chih-Jen Yen

Inventor： Chiu-Hung Cheng ,  Chih-Jen Yen

IPC: H03L7/06

CPC classification number: H03L7/0898 ,  H03L7/107 ,  H03L7/1072 ,  H03L7/18

Abstract: A method for reducing phase lock time and jittering and a phase lock loop (PLL) using the same adapted for PLL including a charge pump (CP) which includes a pull-up and a pull-down networks used for controlling output voltage of the CP. The output voltage is used for controlling frequency and phase of an output signal of the PLL. The method includes: receiving a reference and a feedback signals; setting the driving capabilities of the pull-up and the pull-down networks to a first driving capability when the phase difference between the reference and the feedback signals is greater than a predetermined value; setting the driving capabilities of the pull-up and the pull-down networks to a second driving capability when the phase difference between the reference and the feedback signals is smaller than the predetermined value, wherein the first driving capability is greater than the second driving capability.

Abstract translation: 一种减少相位锁定时间和抖动的方法以及使用适用于PLL的相位锁相环（PLL）的方法，该PLL包括电荷泵（CP），其包括用于控制CP的输出电压的上拉和下拉网络 。 输出电压用于控制PLL输出信号的频率和相位。 该方法包括：接收参考和反馈信号; 当参考和反馈信号之间的相位差大于预定值时，将上拉和下拉网络的驱动能力设置为第一驱动能力; 当基准和反馈信号之间的相位差小于预定值时，将上拉和下拉网络的驱动能力设定为第二驱动能力，其中第一驱动能力大于第二驱动能力 。

公开(公告)号：US20060125463A1

公开(公告)日：2006-06-15

申请号：US11160135

申请日：2005-06-10

Applicant: Chih-Jen Yen ,  Chiu-Hung Cheng

Inventor： Chih-Jen Yen ,  Chiu-Hung Cheng

IPC: G05F3/20

CPC classification number: G05F3/262

Abstract: A voltage-controlled current source (VCCS) is provided. The VCCS controls an output current according to a controlling voltage. The VCCS includes an operational amplifier (OP-amplifier), a transistor, a resistor and a current mirror. The present invention utilizes the characteristics of the OP-amplifier to compensate for the voltage difference between the gate and the source of the transistor so that the resulting terminal voltage on the resistor is equal to the input control voltage. Therefore, the VCCS of the present invention can reduce the factors including process drift, fluctuation in the DC voltage source or the output current that can affect the terminal voltage difference of the resistor and hence the accuracy of the output current.

Abstract translation: 提供压控电流源（VCCS）。 VCCS根据控制电压控制输出电流。 VCCS包括运算放大器（OP放大器），晶体管，电阻和电流镜。 本发明利用OP放大器的特性来补偿晶体管的栅极和源极之间的电压差，使得电阻器上产生的端子电压等于输入控制电压。 因此，本发明的VCCS可以减少影响电阻端子电压差的工艺漂移，直流电压源的波动或输出电流的因素，从而降低输出电流的精度。

公开(公告)号：US07417415B2

公开(公告)日：2008-08-26

申请号：US11160135

申请日：2005-06-10

Applicant: Chih-Jen Yen ,  Chiu-Hung Cheng

Inventor： Chih-Jen Yen ,  Chiu-Hung Cheng

IPC: G05F1/40 ,  G05F1/56

CPC classification number: G05F3/262

Abstract: A voltage-controlled current source (VCCS) is provided. The VCCS controls an output current according to a controlling voltage. The VCCS includes an operational amplifier (OP-amplifier), a transistor, a resistor and a current mirror. The present invention utilizes the characteristics of the OP-amplifier to compensate for the voltage difference between the gate and the source of the transistor so that the resulting terminal voltage on the resistor is equal to the input control voltage. Therefore, the VCCS of the present invention can reduce the factors including process drift, fluctuation in the DC voltage source or the output current that can affect the terminal voltage difference of the resistor and hence the accuracy of the output current.

Abstract translation: 提供压控电流源（VCCS）。 VCCS根据控制电压控制输出电流。 VCCS包括运算放大器（OP放大器），晶体管，电阻和电流镜。 本发明利用OP放大器的特性来补偿晶体管的栅极和源极之间的电压差，使得电阻器上产生的端子电压等于输入控制电压。 因此，本发明的VCCS可以减少影响电阻端子电压差的工艺漂移，直流电压源的波动或输出电流的因素，从而降低输出电流的精度。