Method for implicit addressing of electronic units and corresponding units

    公开(公告)号:US11860801B2

    公开(公告)日:2024-01-02

    申请号:US17422681

    申请日:2019-01-15

    申请人: Christoph Heldeis

    发明人: Christoph Heldeis

    IPC分类号: G06F12/02 G06F13/16 G06F3/14

    CPC分类号: G06F13/1668 G06F3/14

    摘要: A method for implicit addressing includes providing within a first unit and a second unit respectively a counter unit, a comparison unit and a storing unit for the storage of an identifier, allocating a first identifier to the first unit, allocating a second identifier to the second unit setting the same counter value in the counter units of both units, after setting the counter values comparing the counter value in the first unit to the first identifier and comparing the counter value in the second unit to the second identifier, based on equality of the comparison in the first unit sending of first data from the first unit or-assigning of first data to the first unit, based on inequality of the comparison in the second unit no sending or assigning of data to the second unit, and counting up or down the counter value in both units.

    OPTICAL OUTPUT DEVICE, BUS UNIT, BUS CONTROL UNIT AND METHODS

    公开(公告)号:US20220121606A1

    公开(公告)日:2022-04-21

    申请号:US17422666

    申请日:2019-01-15

    申请人: Christoph HELDEIS

    IPC分类号: G06F13/42 G06F13/40

    摘要: An optical output device is described that includes one bus system. The bus system includes two bus wires of a bus, two bus units and one bus control unit. The two bus units may include one optical output element one output control unit whose output is connected to the one optical output element a first storage unit for storing address data of the respective bus unit a second storage unit for storing a counter value, a comparison unit whose inputs are connected to the first storage unit and to the second storage unit, and a control unit whose input is connected to an output of the comparison unit and which controls the takeover of data from the bus into the output control unit depending on an output signal or on output data of the comparison unit.

    METHOD FOR ALLOCATING ADDRESSES AND CORRESPONDING UNITS

    公开(公告)号:US20220065928A1

    公开(公告)日:2022-03-03

    申请号:US17422701

    申请日:2019-01-15

    申请人: Christoph HELDEIS

    摘要: A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected for the second unit to a second address for the second unit.

    METHOD FOR IMPLICIT ADDRESSING OF ELECTRONIC UNITS AND CORRESPONDING UNITS

    公开(公告)号:US20220114119A1

    公开(公告)日:2022-04-14

    申请号:US17422681

    申请日:2019-01-15

    申请人: Christoph HELDEIS

    IPC分类号: G06F13/16 G06F3/14

    摘要: A method for implicit addressing includes providing within a first unit and a second unit respectively a counter unit, a comparison unit and a storing unit for the storage of an identifier, allocating a first identifier to the first unit, allocating a second identifier to the second unit setting the same counter value in the counter units of both units, after setting the counter values comparing the counter value in the first unit to the first identifier and comparing the counter value in the second unit to the second identifier, based on equality of the comparison in the first unit sending of first data from the first unit or-assigning of first data to the first unit, based on inequality of the comparison in the second unit no sending or assigning of data to the second unit, and counting up or down the counter value in both units.

    Method for determining active input elements of an input arrangement and input arrangement

    公开(公告)号:US09876510B2

    公开(公告)日:2018-01-23

    申请号:US14768121

    申请日:2014-02-21

    申请人: Christoph Heldeis

    IPC分类号: H03M11/00 H03M11/20

    CPC分类号: H03M11/003 H03M11/20

    摘要: The invention relates in an aspect A to a method for determining active input elements (S1a, S2a) of an input arrangement (10), comprising providing input elements (S1a to S2b) that are connected according to a matrix arrangement, providing within the matrix arrangement at least two drive lines (L1, L2) that are each connected to a respective driving circuit (2, 4), providing within the matrix arrangement at least two sense lines (Ca, Cb) that may be used to detect active input elements (S1a, S2a), providing within the matrix arrangement serial connections (SC1 to SC4) each comprising one of the input elements (S1a) and a resistor (R1a) and each serial connection (SC1 to SC4) being connected to a respective one of the drive lines (L1, L2) and to a respective one of the sense lines (Ca, Cb), providing pull resistors (Ra, Rb) that connect the sense lines (Ca, Cb) to a first potential, and using a control device for the driving circuits that drives an active drive line (L1) to a second potential that is different from the first potential and that drives a non active drive line (L2) or non active drive lines to the first potential or to a potential having an absolute offset value from the first potential that is at most 50 percent or at most 10 percent of the absolute value of the difference of the first potential and of the second potential.

    DEVICE, PREFERABLY USB DEVICE, CORRESPONDING COMPUTER DEVICE AND METHOD

    公开(公告)号:US20230409513A1

    公开(公告)日:2023-12-21

    申请号:US18247830

    申请日:2020-10-07

    申请人: Christoph HELDEIS

    发明人: Christoph HELDEIS

    IPC分类号: G06F13/42 G06F13/38

    摘要: A device, preferably USB device, including at least one memory unit which is configured to store a firmware program including instructions and at least one interface unit which is configured to forward data to a main processing device according to the USB specification. At least one processor which is configured to perform the instructions of the firmware program, wherein the processor is configured to be externally triggered by trigger events to send at least one data packet including the data to be forwarded via the interface unit.

    Method for allocating addresses and corresponding units

    公开(公告)号:US11835577B2

    公开(公告)日:2023-12-05

    申请号:US17422701

    申请日:2019-01-15

    申请人: Christoph Heldeis

    发明人: Christoph Heldeis

    摘要: A method includes providing a first and second electronic unit unit, generating a wirelessly transmitted signal for detecting or generating one signal or several signals for detection on a chain of electronic elements, for the first unit, detecting a transmission time of the wirelessly transmitted signal for detection or detecting a first transmission time on a first of the chain, for the second unit, detecting a second value or the transmission time of the wirelessly transmitted signal for detection or detecting a second value or a second transmission time on a second position of the chain that is different from the first position, converting the first value or the transmission time detected for the first unit to a first address for the first unit, and converting the second value or the transmission time detected within or for the second unit to a second address for the second unit.

    METHOD FOR DETERMINING ACTIVE INPUT ELEMENTS OF AN INPUT ARRANGEMENT AND INPUT ARRANGEMENT
    8.
    发明申请
    METHOD FOR DETERMINING ACTIVE INPUT ELEMENTS OF AN INPUT ARRANGEMENT AND INPUT ARRANGEMENT 有权
    用于确定输入布置和输入布置的有效输入元件的方法

    公开(公告)号:US20160013806A1

    公开(公告)日:2016-01-14

    申请号:US14768121

    申请日:2014-02-21

    申请人: Christoph HELDEIS

    IPC分类号: H03M11/00 H03M11/20

    CPC分类号: H03M11/003 H03M11/20

    摘要: The invention relates in an aspect A to a method for determining active input elements (S1a, S2a) of an input arrangement (10), comprising providing input elements (S1a to S2b) that are connected according to a matrix arrangement, providing within the matrix arrangement at least two drive lines (L1, L2) that are each connected to a respective driving circuit (2, 4), providing within the matrix arrangement at least two sense lines (Ca, Cb) that may be used to detect active input elements (S1a, S2a), providing within the matrix arrangement serial connections (SC1 to SC4) each comprising one of the input elements (S1a) and a resistor (R1a) and each serial connection (SC1 to SC4) being connected to a respective one of the drive lines (L1, L2) and to a respective one of the sense lines (Ca, Cb), providing pull resistors (Ra, Rb) that connect the sense lines (Ca, Cb) to a first potential, and using a control device for the driving circuits that drives an active drive line (L1) to a second potential that is different from the first potential and that drives a non active drive line (L2) or non active drive lines to the first potential or to a potential having an absolute offset value from the first potential that is at most 50 percent or at most 10 percent of the absolute value of the difference of the first potential and of the second potential.

    摘要翻译: 本发明在一方面A涉及一种用于确定输入装置(10)的有源输入元件(S1a,S2a)的方法,其包括提供根据矩阵布置连接的输入元件(S1a至S2b),在矩阵内提供 布置至少两个驱动线(L1,L2),每个驱动线路(L1,L2)各自连接到相应的驱动电路(2,4),在矩阵布置内提供至少两条感测线(Ca,Cb),其可用于检测有源输入元件 (S1a,S2a),在矩阵布置中提供每个包括输入元件(S1a)和电阻器(R1a)之一的串行连接(SC1至SC4),并且每个串行连接(SC1至SC4)连接到 驱动线(L1,L2)和感测线(Ca,Cb)中的相应一个,提供将感测线(Ca,Cb)连接到第一电位的拉电阻(Ra,Rb),并且使用控制 用于将驱动有源驱动线(L1)驱动到第二波段的驱动电路的装置 其不同于第一电位,并且将非活动驱动线(L2)或非有源驱动线驱动到第一电位或具有绝对偏移值的电位,该绝对偏移值与第一电位最多为50%或最多 第一个电位和第二个电位差的绝对值的10%。

    Optical output device, bus unit, bus control unit and methods

    公开(公告)号:US11928069B2

    公开(公告)日:2024-03-12

    申请号:US17422666

    申请日:2019-01-15

    申请人: Christoph Heldeis

    发明人: Christoph Heldeis

    IPC分类号: G06F13/20 G06F13/40 G06F13/42

    CPC分类号: G06F13/4221 G06F13/4022

    摘要: An optical output device is described that includes one bus system. The bus system includes two bus wires of a bus, two bus units and one bus control unit. The two bus units may include one optical output element one output control unit whose output is connected to the one optical output element a first storage unit for storing address data of the respective bus unit a second storage unit for storing a counter value, a comparison unit whose inputs are connected to the first storage unit and to the second storage unit, and a control unit whose input is connected to an output of the comparison unit and which controls the takeover of data from the bus into the output control unit depending on an output signal or on output data of the comparison unit.

    INPUT DEVICE, PREFERABLY A COMPUTER MOUSE DEVICE, AND METHOD FOR ADJUSTING A PARAMETER FOR SIGNAL DETECTION USING AN INPUT DEVICE

    公开(公告)号:US20240028142A1

    公开(公告)日:2024-01-25

    申请号:US18280897

    申请日:2021-03-09

    申请人: Christoph HELDEIS

    发明人: Christoph HELDEIS

    IPC分类号: G06F3/038 G06F3/0354

    CPC分类号: G06F3/038 G06F3/03543

    摘要: Disclosed is an input device (I, 710), preferably a computer mouse (710), comprising: —a memory unit (M) for storing at least one parameter value (D1 to D6), wherein the at least one parameter value (D1 to D6) defines how an electrical signal (310) that is generated during a user input operation has to be processed within the input device (1, 710), a change signal generation unit comprising at least one of:—a receiving unit (720) that is configured to receive a modification value from outside of the input device (I, 710), —at least one input element (717) that is configured to receive a modification value input by a user, wherein the modification value input is processed directly within the input device (I, 710), —or a modification value generating unit that is configured to generate a modification value within the input device (I, 710), wherein the change signal generation unit is configured to generate a change signal depending on the modification value, and —a control unit (718) that is configured to change the at least one parameter value (D1 to D6) during the operation phase depending on the change signal.