公开(公告)号：US6047351A

公开(公告)日：2000-04-04

申请号：US989365

申请日：1997-12-12

Applicant: Chuck Cheuk-wing Cheng

Inventor： Chuck Cheuk-wing Cheng

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F9/30

CPC classification number: G06F9/30058 ,  G06F9/3804 ,  G06F9/3861 ,  G06F9/4812

Abstract: A microcontroller including a streamlined pipeline processor provides a predictable time period for executing a set of instructions including branch instructions. The microcontroller has a program counter, branch stack and pipeline stages that can be loaded in a single cycle, and allows only the execution stage of the pipeline to alter the CPU state. Thus, the instructions in stages preceding the execution stage can be annulled, and the necessary registers can be updated in the first cycle upon determination of a branch instruction. In subsequent cycles, instructions in the branch routine will flow through the pipeline, one stage per cycle. Thus, a fixed period for responding to a branch instruction is provided. A fixed period for responding to an interrupt is also provided, as is a selectable interrupt schedule for predictable instruction execution in a multi-tasking operation.

Abstract translation: 包括精简流水线处理器的微控制器提供用于执行包括分支指令的一组指令的可预测时间段。 微控制器具有可以在单个周期中加载的程序计数器，分支堆栈和流水线级，并且只允许管道的执行级改变CPU状态。 因此，在执行阶段之前的阶段的指令可以被取消，并且在确定分支指令时可以在第一周期中更新必要的寄存器。 在随后的循环中，分支程序中的指令将流过管道，每个循环一个阶段。 因此，提供了用于响应分支指令的固定周期。 还提供了用于响应中断的固定周期，以及在多任务操作中可预测的指令执行的可选中断调度。

公开(公告)号：US5894549A

公开(公告)日：1999-04-13

申请号：US989935

申请日：1997-12-12

Applicant: Chuck Cheuk-wing Cheng

Inventor： Chuck Cheuk-wing Cheng

IPC: G06F11/10 ,  G11C7/00 ,  G11C13/00

CPC classification number: G06F11/1008

Abstract: A method for fault detection in microcontroller program memory includes a new move instruction. An address of program instruction data is placed in a word register and a mode register. The new address points to a new instruction in a program memory. The program instruction data is read from the program memory into an instruction register and then transferred from the instruction register to the word register and the mode register. The contents of the word register and the mode register are then written to a data memory. With the program instruction data now available in the data memory, the new instruction can be tested for data integrity and validity using, for example, fault detection mechanisms or processes. A system for fault detection to check instructions or data in the program memory for data integrity and validity in a program memory also is disclosed.

Abstract translation: 微控制器程序存储器中的故障检测方法包括新的移位指令。 程序指令数据的地址被放置在字寄存器和模式寄存器中。 新地址指向程序存储器中的新指令。 程序指令数据从程序存储器读入指令寄存器，然后从指令寄存器传送到字寄存器和模式寄存器。 然后将字寄存器和模式寄存器的内容写入数据存储器。 利用数据存储器中现有的程序指令数据，可以使用例如故障检测机制或过程来测试新指令的数据完整性和有效性。 公开了一种用于在程序存储器中检查程序存储器中的数据完整性和有效性的指令或数据的故障检测系统。

公开(公告)号：US06353880B1

公开(公告)日：2002-03-05

申请号：US09121224

申请日：1998-07-22

Applicant: Chuck Cheuk-wing Cheng

Inventor： Chuck Cheuk-wing Cheng

IPC: G06F930

CPC classification number: G06F9/3834 ,  G06F9/3867

Abstract: A system and method for efficiently processing instructions in a pipeline architecture for a microcontroller and maintaining a fixed instruction execution per clock cycle rate is disclosed. The pipeline comprises four stages: an instruction fetch stage, an operand fetch stage, an execution stage, and a write back stage. In a first embodiment, an entire clock cycle is dedicated to the instruction fetch stage to the instruction fetch stage to retrieve instruction data from non-volatile memory in a single clock cycle. In a second embodiment, the operand fetch stage preliminarily decodes the instruction data to determine tasks to be performed to allow the execution stage to perform its time-intensive calculations in a single clock cycle. Additionally, the operand fetch stage initiates the performance of tasks determined from the decoding of the instructions to minimize the time required to perform those tasks by the execution stage. In one embodiment, a read address is generated responsive to determining that a read operation is to be performed by the execution stage. In a third embodiment, a dual port data memory is employed to allow the execution stage and the write back stage to perform read and write operations concurrently, in a single clock cycle. Additional embodiments are disclosed for addressing circumstances in which one stage modifies the data address pointer required by another stage or one stage writes to an data memory location required for a read operation by a previous stage. Thus, a one instruction per clock cycle rate is achieved and maintained.

Abstract translation: 公开了一种用于在微控制器的流水线架构中有效处理指令并维持每个时钟周期速率的固定指令执行的系统和方法。 流水线包括四个阶段：指令提取阶段，操作数获取阶段，执行阶段和回写阶段。 在第一实施例中，整个时钟周期专用于指令提取级，以在单个时钟周期内从非易失性存储器检索指令数据。 在第二实施例中，操作数获取阶段预先对指令数据进行解码以确定要执行的任务，以允许执行阶段在单个时钟周期内执行其时间密集的计算。 此外，操作数获取阶段启动从指令解码确定的任务的执行，以最小化执行阶段执行这些任务所需的时间。 在一个实施例中，响应于确定执行阶段执行读取操作而产生读取地址。 在第三实施例中，采用双端口数据存储器来允许执行级和写回级在单个时钟周期内同时执行读和写操作。 公开了另外的实施例，用于解决一个阶段修改另一个阶段所需的数据地址指针或一个阶段向前一阶段的读取操作所需的数据存储器位置写入的情况。 因此，实现并保持每个时钟周期速率的一个指令。

公开(公告)号：US06243804B1

公开(公告)日：2001-06-05

申请号：US09121201

申请日：1998-07-22

Applicant: Chuck Cheuk-wing Cheng

Inventor： Chuck Cheuk-wing Cheng

IPC: G06F948

CPC classification number: G06F9/30116 ,  G06F9/30123 ,  G06F9/3863

Abstract: A system and method for efficiently handling interrupts in a microcontroller environment is disclosed. An interrupt handling circuit preserves a current state of a microcontroller comprising a plurality of primary registers for storing information relating to the current state of the microcontroller and a plurality of shadow registers coupled to at least two of the primary registers for storing the information contained in the coupled primary registers in response to receiving an interrupt enter signal from an interrupt signal generator. In one embodiment the information relating to the current state of the microcontroller includes the program counter, accumulator data, CPU status data, and an address pointer to data memory. In a preferred embodiment, the information is restored to the primary registers within one clock cycle of receiving an interrupt exit signal from the interrupt signal generator. In a pipeline stage embodiment a sequence of interrupt instructions is fed into the pipeline in subsequent clock cycles after the data is stored in the shadow registers, facilitating a rapid response to the interrupt.

Abstract translation: 公开了一种用于在微控制器环境中高效地处理中断的系统和方法。 中断处理电路保持微控制器的当前状态，该微控制器包括用于存储与微控制器的当前状态相关的信息的多个主寄存器，以及耦合到至少两个主寄存器的多个影子寄存器，用于存储包含在 响应于从中断信号发生器接收到中断输入信号，耦合的主寄存器。 在一个实施例中，与微控制器的当前状态相关的信息包括程序计数器，累加器数据，CPU状态数据和到数据存储器的地址指针。 在优选实施例中，在从中断信号发生器接收中断退出信号的一个时钟周期内，信息被恢复到初级寄存器。 在流水线级实施例中，在将数据存储在影子寄存器中之后的后续时钟周期中，中断指令序列被馈送到流水线中，便于对中断的快速响应。

公开(公告)号：US5949728A

公开(公告)日：1999-09-07

申请号：US989936

申请日：1997-12-12

Applicant: Kwo-Jen Liu ,  Chuck Cheuk-Wing Cheng

Inventor： Kwo-Jen Liu ,  Chuck Cheuk-Wing Cheng

IPC: G11C7/06 ,  G11C16/28 ,  G11C7/00

CPC classification number: G11C16/28 ,  G11C7/067

Abstract: A single ended sensing scheme amplifies the logic state stored within a non-volatile memory circuit by relying upon three stages, a clamping circuit, a first operational amplifier and a second operational amplifier. The clamping circuit clamps the voltage at a voltage level with a small voltage swing between the logic states. The first stage and second stage operational amplifiers increase the clamped voltage level. A reference memory circuit ensures that the sensing scheme output is properly adjusted to compensate for voltage and temperature variations as well as noise injection from the power supply and ground.

Abstract translation: 单端感测方案通过依靠三个阶段来放大存储在非易失性存储器电路内的逻辑状态，钳位电路，第一运算放大器和第二运算放大器。 钳位电路在逻辑状态之间以小的电压摆幅将电压钳位在电压电平。 第一级和第二级运算放大器增加了钳位电压电平。 参考存储器电路确保感测方案输出被适当地调整以补偿电压和温度变化以及来自电源和接地的噪声注入。