公开(公告)号：US5949728A

公开(公告)日：1999-09-07

申请号：US989936

申请日：1997-12-12

Applicant: Kwo-Jen Liu ,  Chuck Cheuk-Wing Cheng

Inventor： Kwo-Jen Liu ,  Chuck Cheuk-Wing Cheng

IPC: G11C7/06 ,  G11C16/28 ,  G11C7/00

CPC classification number: G11C16/28 ,  G11C7/067

Abstract: A single ended sensing scheme amplifies the logic state stored within a non-volatile memory circuit by relying upon three stages, a clamping circuit, a first operational amplifier and a second operational amplifier. The clamping circuit clamps the voltage at a voltage level with a small voltage swing between the logic states. The first stage and second stage operational amplifiers increase the clamped voltage level. A reference memory circuit ensures that the sensing scheme output is properly adjusted to compensate for voltage and temperature variations as well as noise injection from the power supply and ground.

Abstract translation: 单端感测方案通过依靠三个阶段来放大存储在非易失性存储器电路内的逻辑状态，钳位电路，第一运算放大器和第二运算放大器。 钳位电路在逻辑状态之间以小的电压摆幅将电压钳位在电压电平。 第一级和第二级运算放大器增加了钳位电压电平。 参考存储器电路确保感测方案输出被适当地调整以补偿电压和温度变化以及来自电源和接地的噪声注入。

公开(公告)号：US06806142B1

公开(公告)日：2004-10-19

申请号：US10604263

申请日：2003-07-07

Applicant: An-Ru Cheng ,  Kwo-Jen Liu ,  Chih-Hung Chen

Inventor： An-Ru Cheng ,  Kwo-Jen Liu ,  Chih-Hung Chen

IPC: H01L218234

CPC classification number: H01L27/11226 ,  H01L27/112

Abstract: A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array and all transistors are initially in an “ON” state. A second dielectric layer covers at least one layer of metal interconnection formed over the first dielectric layer. The bit lines do not overlap the transistor-sources. A coding photoresist layer is formed on the second dielectric layer and is patterned to form a plurality of apertures defining exposure windows exposing underlying field-effect transistors to be coded permanently to an “OFF” state. A code etching back process is implemented using the photoresist layer as a mask to etch the first and second dielectric layers, the sources of the MOSFETs, and a portion of the substrate through the exposure windows to form a deep trench, disconnecting the coded MOSFETs from the source lines.

Abstract translation: 一种用于制造ROM器件的方法包括：具有ROM区域内的场效应晶体管阵列的半导体衬底。 第一介电层覆盖阵列，并且所有晶体管最初处于“接通”状态。 第二介电层覆盖形成在第一介电层上的至少一层金属互连层。 位线不与晶体管源重叠。 编码光致抗蚀剂层形成在第二电介质层上，并且被图案化以形成限定曝光窗口的多个孔，暴露下来的场效应晶体管被永久地编码为“关”状态。 使用光致抗蚀剂层作为掩模来实现代码蚀刻反向工艺，以通过曝光窗口蚀刻第一和第二介电层，MOSFET的源和衬底的一部分，以形成深沟槽，从而将编码的MOSFET从 源码行。

公开(公告)号：US06756275B1

公开(公告)日：2004-06-29

申请号：US10249286

申请日：2003-03-28

Applicant: Kwo-Jen Liu ,  Chih-Hung Chen ,  An-Ru Cheng

Inventor： Kwo-Jen Liu ,  Chih-Hung Chen ,  An-Ru Cheng

IPC: H01L218236

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A method for manufacturing a ROM device includes a semiconductor substrate having an array of field-effect transistors within a ROM region. A first dielectric layer covers the array of field-effect transistors. All of the field-effect transistors are initially in an “ON” state having a threshold voltage at a first value. At least one layer of metal interconnection is formed over the first dielectric layer within the ROM region and Is covered by a second dielectric layer. A coding photoresist layer is formed on the second dielectric layer and patterned to form a plurality of apertures defining exposure windows. Using the patterning coding photoresist layer as a dielectric etching and implantation hard mask, the underlying field-effect transistors to be coded permanently to a logic “OFF” state through the apertures, thereby raising the threshold voltage of the field-effect transistors to a second value.

Abstract translation: 一种用于制造ROM器件的方法包括：具有ROM区域内的场效应晶体管阵列的半导体衬底。 第一介电层覆盖场效应晶体管阵列。 所有场效应晶体管初始处于具有第一值的阈值电压的“导通”状态。 在ROM区域内的第一介电层上形成至少一层金属互连，并被第二介电层覆盖。 编码光致抗蚀剂层形成在第二电介质层上并被图案化以形成限定曝光窗口的多个孔。 使用图案化编码光致抗蚀剂层作为电介质蚀刻和注入硬掩模，下面的场效应晶体管将通过孔径永久地编码为逻辑“关”状态，从而将场效应晶体管的阈值电压提高到第二 值。

公开(公告)号：US06252813B1

公开(公告)日：2001-06-26

申请号：US09477223

申请日：2000-01-04

Applicant: Kwo-Jen Liu

Inventor： Kwo-Jen Liu

IPC: G11C700

CPC classification number: G11C17/12

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract translation: 一种在低工作电压下具有高速差分感测的可编程只读存储器的方法和装置。 在一个实施例中，可编程存储单元由字线，位线和晶体管组成。 表示单个二进制数位（位）的晶体管具有耦合到字线的栅极，耦合到位线的漏极和能够被编程以提供逻辑电平0并且逻辑电平为1的源。通过 对晶体管的源极进行编程，逻辑电平0和逻辑电平1状态之间的位线几乎相等。

公开(公告)号：US06188265B1

公开(公告)日：2001-02-13

申请号：US08989846

申请日：1997-12-12

Applicant: Kwo-Jen Liu ,  Chuck Cheng-Wing Cheng

Inventor： Kwo-Jen Liu ,  Chuck Cheng-Wing Cheng

IPC: H03K1716

CPC classification number: H03K17/063 ,  G11C5/145 ,  G11C16/12

Abstract: A high voltage NMOS switch is adjustable in order to optimize the switch for proper operation with different circuit configurations. A high voltage booster, included within the high voltage NMOS switch, enables the switch to reclaim the previously unused second half-cycle of a power source waveform signal, which thereby increases the speed of the NMOS switch by a factor of two. In addition, the high voltage NMOS switch provides added ramp rate flexibility by enabling a user to optimize the ramp rate of the high voltage NMOS switch for different circuit configurations.

Abstract translation: 高电压NMOS开关是可调节的，以便优化开关，以便不同的电路配置正常工作。 包括在高压NMOS开关内的高压升压器使得开关能够回收先前未使用的电源波形信号的第二半周期，从而将NMOS开关的速度提高了2倍。 此外，高电压NMOS开关通过使用户能够优化用于不同电路配置的高压NMOS开关的斜坡率来提供附加的斜坡率灵活性。

公开(公告)号：US5796670A

公开(公告)日：1998-08-18

申请号：US745101

申请日：1996-11-07

Applicant: Kwo-Jen Liu

Inventor： Kwo-Jen Liu

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C14/00

Abstract: A nonvolatile memory cell for a random access memory device is provided. The invented memory cells are similar in configuration to the memory cells of known DRAM devices, so that DRAM devices embodying the invented cells may replace existing DRAM devices. The invented nonvolatile cell also affords a memory device that has low cost of manufacture, high data storage capacity, and low power consumption. Each memory cell includes a floating layer of polysilicon that is interposed between a reference voltage source and a node polysilicon. The floating polysilicon provides nonvolatile storage of data previously stored on the node polysilicon. An electron charge stored on the node polysilicon is transferred to the floating polysilicon, using known electron tunneling methods, before power to the device is removed, so that the data is not lost. When power is reapplied to the device, the data is transferred back to the node polysilicon from the floating polysilicon, so that the data can be accessed as if the data were stored in a conventional DRAM device. With the invented memory cells, data is accessed and manipulated substantially faster than known nonvolatile memory devices. Additionally, an insulating oxide layer is interposed between the floating polysilicon and the reference voltage source, for reducing leakage current from the floating polysilicon to the reference voltage source. This enhances the ability of the floating polysilicon to retain data thereon.

Abstract translation: 提供了一种用于随机存取存储器件的非易失性存储单元。 本发明的存储器单元在配置上与已知的DRAM器件的存储器单元相似，使得体现本发明的单元的DRAM器件可以替代现有的DRAM器件。 本发明的非易失性单元还提供了具有低制造成本，高数据存储容量和低功耗的存储器件。 每个存储单元包括介于参考电压源和节点多晶硅之间的浮置多晶硅层。 浮置多晶硅提供了先前存储在节点多晶硅上的数据的非易失性存储。 使用已知的电子隧道法将存储在节点多晶硅上的电子电荷转移到浮置多晶硅，在去除器件的电源被去除之前，使得数据不会丢失。 当电源重新应用于器件时，数据从浮置多晶硅转移回节点多晶硅，从而数据可以像数据存储在常规DRAM器件中那样被访问。 利用本发明的存储器单元，数据被访问和操作比已知的非易失性存储器件快得多。 此外，在浮置多晶硅和参考电压源之间插入绝缘氧化物层，用于减少从浮置多晶硅到参考电压源的泄漏电流。 这增加了浮动多晶硅在其上保留数据的能力。

公开(公告)号：US5476803A

公开(公告)日：1995-12-19

申请号：US323756

申请日：1994-10-17

Applicant: Kwo-Jen Liu

Inventor： Kwo-Jen Liu

IPC: H01L21/336 ,  H01L21/60 ,  H01L21/823

CPC classification number: H01L21/76897 ,  H01L29/6659

Abstract: A method for fabricating semiconductor devices with a self-spaced contact is provided. Spacing required between the self-spaced contact and a gate region is lessened, thus reducing chip size, and parasitic capacitance and resistance. A transistor region includes a gate and diffusion region. A pad oxide layer comprises an uppermost layer of the gate. A spacer oxide is formed on side walls of the gate region. The thickness of the pad oxide layer controls the width of the spacer oxide region. The spacer oxide insulates the gate from the diffusion regions, so that electrical contacts may be formed close to the gate for reducing the overall size of the semiconductor device. The doping structure of the diffusion regions is controlled by the width of the spacer oxide regions. Thus, the doping structure of the diffusions can be altered to reduce parasitic capacitance and resistance.

Abstract translation: 提供了一种用于制造具有自分隔接触的半导体器件的方法。 自隔离触点和栅极区之间所需的间距减小，从而减小芯片尺寸以及寄生电容和电阻。 晶体管区域包括栅极和扩散区域。 衬垫氧化物层包括栅极的最上层。 在栅极区域的侧壁上形成间隔氧化物。 衬垫氧化物层的厚度控制间隔氧化物区域的宽度。 间隔氧化物使栅极与扩散区绝缘，使得电触点可以靠近栅极形成，以减小半导体器件的整体尺寸。 扩散区域的掺杂结构由间隔氧化物区域的宽度来控制。 因此，可以改变扩散的掺杂​​结构以减小寄生电容和电阻。

公开(公告)号：US07889541B2

公开(公告)日：2011-02-15

申请号：US12422078

申请日：2009-04-10

Applicant: Wei-Chiang Shih ,  Chen-Hao Po ,  Kwo-Jen Liu

Inventor： Wei-Chiang Shih ,  Chen-Hao Po ,  Kwo-Jen Liu

IPC: G11C11/00

CPC classification number: G11C11/412 ,  G11C11/413

Abstract: A SRAM cell structure includes a first N type switch, a second N type switch, a first storage node, and a second storage node. The first N type switch has a control terminal connected to a word line and a first terminal connected to a bit line. The second N type switch has a control terminal connected to the word line and a first terminal connected to an inverted bit line. The first storage node has a first terminal connected to a second terminal of the first N type switch. The second storage node has a first terminal connected to a second terminal of the second N type switch.

Abstract translation: SRAM单元结构包括第一N型交换机，第二N型交换机，第一存储节点和第二存储节点。 第一N型开关具有连接到字线的控制端子和连接到位线的第一端子。 第二N型开关具有连接到字线的控制端子和连接到反相位线的第一端子。 第一存储节点具有连接到第一N型交换机的第二终端的第一终端。 第二存储节点具有连接到第二N型交换机的第二终端的第一终端。

公开(公告)号：US06819579B1

公开(公告)日：2004-11-16

申请号：US10249588

申请日：2003-04-22

Applicant: Kwo-Jen Liu ,  Hsin-Shih Wang

Inventor： Kwo-Jen Liu ,  Hsin-Shih Wang

IPC: G11C1500

CPC classification number: G11C15/04

Abstract: A novel ten-transistor (10-T) content addressable memory (CAM) cell and an integrated CAM architecture. A six-transistor (6-T) static random access memory (SRAM), cell and a four-transistor (4-T) comparator module of the 10-T CAM cell are respectively coupled to different bit lines for preventing any disturbance at a match line associated with the 10-T CAM. Each row of the integrated CAM architecture includes a valid bit cell combined with a protect bit cell and at least a mask cell with global resetting function to sufficiently ensure the correction and flexibility during comparing operations.

Abstract translation: 一种新颖的十晶体管（10-T）内容可寻址存储器（CAM）单元和集成CAM架构。 10-T CAM单元的六晶体管（6-T）静态随机存取存储器（SRAM），单元和四晶体管（4-T）比较器模块分别耦合到不同的位线，以防止在 与10-T CAM相关的匹配线。 集成CAM架构的每一行包括与保护位单元组合的有效位单元和至少具有全局复位功能的掩模单元，以充分确保在比较操作期间的校正和灵活性。

公开(公告)号：US06185147B2

公开(公告)日：2001-02-06

申请号：US09478243

申请日：2000-01-04

Applicant: Kwo-Jen Liu

Inventor： Kwo-Jen Liu

IPC: G11C800

CPC classification number: G11C17/12

Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.

Abstract translation: 一种在低工作电压下具有高速差分感测的可编程只读存储器的方法和装置。 在一个实施例中，可编程存储单元由字线，位线和晶体管组成。 表示单个二进制数位（位）的晶体管具有耦合到字线的栅极，耦合到位线的漏极和能够被编程以提供逻辑电平0并且逻辑电平为1的源。通过 对晶体管的源极进行编程，逻辑电平0和逻辑电平1状态之间的位线几乎相等。