公开(公告)号：US07292103B2

公开(公告)日：2007-11-06

申请号：US11107284

申请日：2005-04-14

申请人： Chul Hong Park ,  James Nicholas Wholey

发明人： Chul Hong Park ,  James Nicholas Wholey

IPC分类号： H03G3/10 ,  H03G3/30

CPC分类号： H03G3/3042 ,  H03F1/32 ,  H03F1/565 ,  H03F2200/471

摘要： An amplifier system is provided for amplifying an input signal to provide an amplified output signal, amplifying an amplified input signal to provide a further amplified output signal, and phase delay compensating variations of the amplifications of the amplified output signal and the further amplified output signal for providing the further amplified output signal with substantially linear amplification under a variable load.

摘要翻译： 提供放大器系统，用于放大输入信号以提供放大的输出信号，放大放大的输入信号以提供进一步放大的输出信号，以及相位延迟补偿放大的输出信号的放大和进一步放大的输出信号的变化，以供 在可变负载下提供具有基本上线性放大的进一步放大的输出信号。

公开(公告)号：US07126438B2

公开(公告)日：2006-10-24

申请号：US10848720

申请日：2004-05-19

申请人： Chul Hong Park

发明人： Chul Hong Park

IPC分类号： H03H7/38

CPC分类号： H03H7/40 ,  H01G5/16 ,  H01G5/40 ,  H03H2007/008

摘要： A circuit and method for transmitting an output signal utilizes an inductive device connected in series with a microelectromechanical systems (MEMS) varactor to increase the potential difference across the MEMS varactor due to the output signal by introducing inductance-capacitance resonant behavior. The MEMS varactor is configured to be actuated exclusively by the output signal to effectuate a change in capacitance of the MEMS varactor. The MEMS varactor is used to provide a variable impedance transformation.

摘要翻译： 用于传输输出信号的电路和方法利用与微机电系统（MEMS）变容二极管串联连接的感应装置，以通过引入电感 - 电容谐振行为，由于输出信号而增加跨过MEMS变容二极管的电位差。 MEMS变容二极管被配置为仅由输出信号驱动以实现MEMS变容二极管的电容变化。 MEMS变容二极管用于提供可变阻抗变换。

公开(公告)号：US07053728B2

公开(公告)日：2006-05-30

申请号：US10804356

申请日：2004-03-19

申请人： Chul Hong Park

发明人： Chul Hong Park

IPC分类号： H03H7/38

CPC分类号： H03H7/40 ,  H03H7/383

摘要： An impedance transformation network, power amplifier and method for efficiently transmitting an output signal utilizes a series varactor device to provide a variable impedance transformation. The series varactor device may include a number of stacked ferroelectric varactors that function as a variable capacitor to provide the variable impedance transformation in response to the power level of the output signal.

摘要翻译： 用于有效地传输输出信号的阻抗变换网络，功率放大器和方法利用串联变容二极管装置来提供可变阻抗变换。 串联变容二极管器件可以包括多个堆叠的铁电变阻器，其用作可变电容器以响应于输出信号的功率电平提供可变阻抗变换。

公开(公告)号：US07873929B2

公开(公告)日：2011-01-18

申请号：US11893096

申请日：2007-08-14

申请人： Andrew B. Kahng ,  Chul-Hong Park

发明人： Andrew B. Kahng ,  Chul-Hong Park

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： Method and apparatus for designing an integrated circuit. A new layout is generated for at least one standard cell that incorporates an auxiliary pattern on a gate layer to facilitate cell-based optical proximity correction. An original placement solution is modified for a plurality of standard cells to permit incorporation of cells containing auxiliary patterns while improving an objective function of a resulting placement solution for the plurality of standard cells.

摘要翻译： 用于设计集成电路的方法和装置。 对于在栅极层上并入辅助图案的至少一个标准单元产生新的布局，以促进基于单元的光学邻近校正。 针对多个标准单元修改原始放置解决方案，以允许并入含有辅助图案的单元，同时改善针对多个标准单元的结果放置溶液的目标函数。

公开(公告)号：US07640522B2

公开(公告)日：2009-12-29

申请号：US11331605

申请日：2006-01-14

申请人： Puneet Gupta ,  Andrew B. Kahng ,  Chul-Hong Park

发明人： Puneet Gupta ,  Andrew B. Kahng ,  Chul-Hong Park

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G06F17/5068

摘要： A method and system for detailed placement of layout objects in a standard-cell layout design are disclosed. Layout objects comprise cells and etch dummies. The method includes a programming based technique to calculate layout object perturbation distances for the layout objects. The method includes adjusting the layout objects with their corresponding layout object perturbation distances. This leads to improved photolithographic characteristics such as reduced Critical Dimension (CD) errors and forbidden pitches in the standard-cell layout.

摘要翻译： 公开了一种用于在标准单元布局设计中详细布置布局对象的方法和系统。 布局对象包括单元格和蚀刻虚拟。 该方法包括基于编程的技术来计算布局对象的布局对象扰动距离。 该方法包括使用其对应的布局对象扰动距离调整布局对象。 这导致改进的光刻特性，例如在标准单元布局中减少临界尺寸（CD）误差和禁止间距。

公开(公告)号：US20080235645A1

公开(公告)日：2008-09-25

申请号：US11725396

申请日：2007-03-19

申请人： Andrew B. Kahng ,  Chul-Hong Park ,  Xu Xu

发明人： Andrew B. Kahng ,  Chul-Hong Park ,  Xu Xu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： Method for detecting hotspots in a circuit layout includes constructing a layout graph having nodes, corner edges and proximity edges from the circuit layout, converting the layout graph to a corresponding dual graph, and iteratively selecting edges and nodes having weights greater than a predetermined threshold value at each iteration as hotspots.

摘要翻译： 用于在电路布局中检测热点的方法包括构建具有来自电路布局的节点，拐角边缘和邻近边缘的布局图，将布局图转换为相应的双图，并迭代地选择具有大于预定阈值的权重的边和节点 在每个迭代作为热点。

公开(公告)号：US07097949B2

公开(公告)日：2006-08-29

申请号：US10688591

申请日：2003-10-17

申请人： Dong-Hyun Kim ,  Moon-Hyun Yoo ,  Jeong-Lim Nam ,  Yoo-Hyon Kim ,  Chul-Hong Park ,  Soo-Han Choi ,  Young-Chan Ban ,  Hye-Soo Shin

发明人： Dong-Hyun Kim ,  Moon-Hyun Yoo ,  Jeong-Lim Nam ,  Yoo-Hyon Kim ,  Chul-Hong Park ,  Soo-Han Choi ,  Young-Chan Ban ,  Hye-Soo Shin

IPC分类号： G01F9/00

CPC分类号： G03F1/34 ,  G03F1/70

摘要： A phase edge phase shift mask and a fabrication method thereof for enforcing a width of a field gate image located on a field region, which is weakened by a two exposure process, by using a phase shift mask and a trim mask on a semiconductor substrate, and enforcing a width of the field gate image to maximize a current driving capability of the semiconductor device.

摘要翻译： 一种相位相移掩模及其制造方法，用于通过在半导体衬底上使用相移掩模和修剪掩模来强化位于通过两次曝光处理削弱的场区域上的场栅图像的宽度， 并施加栅极栅极图像的宽度以最大化半导体器件的电流驱动能力。

公开(公告)号：US06984853B2

公开(公告)日：2006-01-10

申请号：US10789301

申请日：2004-02-26

申请人： Chul Hong Park

发明人： Chul Hong Park

IPC分类号： H01L29/739

CPC分类号： H01L29/7785 ,  H01L27/0248 ,  H01L29/66462

摘要： An integrated circuit (IC) with high electron mobility transistors, such as enhancement mode pseudomorphic high electron mobility transistors (E-pHEMTs) and method for fabricating the IC utilizes an increased gate-to-drain etch recess spacing in some of the high electron mobility transistors to provide on-chip electrostatic discharge protection. The use of the increased gate-to-drain etch recess spacing allows smaller high electron mobility transistors to be used for ancillary low speed applications on the IC, which reduces the chip area occupied by these ancillary transistors.

摘要翻译： 具有高电子迁移率晶体管的集成电路（IC），例如增强模拟伪晶体高电子迁移率晶体管（E-pHEMT）以及用于制造IC的方法利用在一些高电子迁移率中增加的栅 - 漏蚀刻凹槽间距 晶体管提供片上静电放电保护。 使用增加的栅极到漏极蚀刻凹槽间隔允许较小的高电子迁移率晶体管用于IC上的辅助低速应用，这降低了这些辅助晶体管占用的芯片面积。

公开(公告)号：US06977562B2

公开(公告)日：2005-12-20

申请号：US10251273

申请日：2002-09-19

申请人： Chul Hong Park

发明人： Chul Hong Park

IPC分类号： H03F3/21 ,  H01P5/04 ,  H03F1/08 ,  H03F3/24 ,  H03H7/40 ,  H03H7/38

CPC分类号： H03H7/40 ,  H01P5/04

摘要： A passive interface circuit for coupling an output signal from a power amplifier to a load is disclosed. The interface presents an impedance to the power amplifier that increases as the power level in the output signal decreases. In one embodiment, the interface circuit includes a fixed network and a capacitor having a capacitance that varies with the potential across the capacitor. The fixed network couples the output signal to the load. The capacitor is connected in parallel with the load and has a capacitance that increases in response to an increase in potential across the capacitor. The capacitor is preferably a MEM capacitor having plates that move with respect to one another in response to changes in the average potential difference between the plates.

摘要翻译： 公开了一种用于将功率放大器的输出信号耦合到负载的无源接口电路。 该接口提供了功率放大器的阻抗，随着输出信号中的功率电平的减小而增加。 在一个实施例中，接口电路包括固定网络和具有随电容器两端的电位而变化的电容的电容器。 固定网络将输出信号耦合到负载。 电容器与负载并联连接，并且具有随着电容器两端的电位增加而增加的电容。 电容器优选地是具有响应于板之间的平均电位差的变化而相对于彼此移动的板的MEM电容器。

公开(公告)号：US20150357282A1

公开(公告)日：2015-12-10

申请号：US14619073

申请日：2015-02-11

申请人： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

发明人： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

摘要翻译： 半导体器件包括衬底; 形成在所述基板上的第一垂直高度的多个导电区域; 第一布线层，其以比第一垂直度高的第二垂直度形成在所述基板上，所述第一布线层包括沿第一方向延伸的第一布线，所述第一布线的一条第一线连接到所选择的第一导电区域 从所述多个导电区域通过通孔接触; 第二布线层，其在高于第二垂直度的第三垂直度处形成在基板上，第二布线层包括沿与第一方向交叉的第二方向延伸的第二线，第二线的一条第二线连接到 从所述多个导电区域中选择的第二导电区域; 以及与第一布线层的线在水平方向上隔开并且从第二导电区延伸到一条第二线的深通孔接触。