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    LOGIC CELL, SEMICONDUCTOR DEVICE INCLUDING LOGIC CELL, AND METHOD OF MANUFACTURING THE LOGIC CELL AND SEMICONDUCTOR DEVICE
    1.
    发明申请
    LOGIC CELL, SEMICONDUCTOR DEVICE INCLUDING LOGIC CELL, AND METHOD OF MANUFACTURING THE LOGIC CELL AND SEMICONDUCTOR DEVICE 有权
    逻辑单元，包括逻辑单元的半导体器件以及制造逻辑单元和半导体器件的方法

    公开(公告)号：US20150357282A1

    公开(公告)日：2015-12-10

    申请号：US14619073

    申请日：2015-02-11

    申请人： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

    发明人： Vincent Chun Fai LAU ,  Jung-ho DO ,  Byung-sung KIM ,  Chul-hong PARK

    IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/088

    CPC分类号： H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/11807 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a substrate; a plurality of conductive areas formed on the substrate at a first vertical level; a first wiring layer formed on the substrate at a second vertical level which is higher than the first vertical level, the first wiring layer including first lines that extend in a first direction, one first line of the first lines connected to a first conductive area selected from the plurality of conductive areas through a via contact; a second wiring layer formed on the substrate at a third vertical level which is higher than the second vertical level, the second wiring layer including second lines that extend in a second direction that crosses the first direction, one second line of the second lines connected to a second conductive area selected from the plurality of conductive areas; and a deep via contact spaced apart from lines of the first wiring layer in a horizontal direction and extending from the second conductive area to the one second line.

    摘要翻译： 半导体器件包括衬底; 形成在所述基板上的第一垂直高度的多个导电区域; 第一布线层，其以比第一垂直度高的第二垂直度形成在所述基板上，所述第一布线层包括沿第一方向延伸的第一布线，所述第一布线的一条第一线连接到所选择的第一导电区域 从所述多个导电区域通过通孔接触; 第二布线层，其在高于第二垂直度的第三垂直度处形成在基板上，第二布线层包括沿与第一方向交叉的第二方向延伸的第二线，第二线的一条第二线连接到 从所述多个导电区域中选择的第二导电区域; 以及与第一布线层的线在水平方向上隔开并且从第二导电区延伸到一条第二线的深通孔接触。