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21 条记录 (耗时 0.018 秒)

    Cross-talk reduction through deep pixel well implant for image sensors
    2.
    发明授权
    Cross-talk reduction through deep pixel well implant for image sensors 有权
    通过图像传感器的深像素阱植入进行串扰减少

    公开(公告)号：US07388187B1

    公开(公告)日：2008-06-17

    申请号：US11682428

    申请日：2007-03-06

    申请人： Han-Chi Liu ,  Chung-Wei Chang ,  Shou-Gwo Wuu ,  Tong-Chern Ong ,  Chun-Yao Ko

    发明人： Han-Chi Liu ,  Chung-Wei Chang ,  Shou-Gwo Wuu ,  Tong-Chern Ong ,  Chun-Yao Ko

    IPC分类号： H01L31/00

    CPC分类号： H01L27/14654 ,  H01L27/1463

    摘要： An image sensor device includes a semiconductor substrate having a first type of conductivity, a semiconductor layer having the first type of conductivity formed on the semiconductor substrate, and pixels formed in the semiconductor layer. The semiconductor layer includes a first deep well having the first type of conductivity and substantially underlying the plurality of pixels, and a second deep well having a second type of conductivity different from the first type of conductivity and substantially underlying the first deep well.

    摘要翻译： 图像传感器装置包括具有第一导电类型的半导体衬底，在半导体衬底上形成具有第一类型导电性的半导体层和形成在半导体层中的像素。 半导体层包括具有第一类型导电性并且基本上位于多个像素下面的第一深阱，以及具有不同于第一类型导电性的第二类型导电性并且基本上位于第一深阱的第二深阱。

    Method and device to reduce dark current in image sensors
    4.
    发明授权
    Method and device to reduce dark current in image sensors 有权
    降低图像传感器暗电流的方法和装置

    公开(公告)号：US07879639B2

    公开(公告)日：2011-02-01

    申请号：US11735226

    申请日：2007-04-13

    申请人： Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

    发明人： Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

    IPC分类号： H01L21/00

    CPC分类号： H01L27/14689 ,  H01L27/14609

    摘要： A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.

    摘要翻译： 制造图像传感器的方法包括提供具有像素区域和逻辑区域的半导体衬底，在像素区域中形成光感测元件，以及在像素区域中形成第一晶体管和在逻辑区域中形成第二晶体管。 在逻辑区域中的像素区域和第二晶体管中形成第一晶体管的步骤包括在像素区域和逻辑区域中执行第一注入处理，在像素区域和逻辑区域中执行第二注入处理，以及执行 仅在逻辑区域中进行第三次植入过程。

    METHOD AND DEVICE TO REDUCE DARK CURRENT IN IMAGE SENSORS
    7.
    发明申请
    METHOD AND DEVICE TO REDUCE DARK CURRENT IN IMAGE SENSORS 有权
    减少图像传感器中的暗电流的方法和装置

    公开(公告)号：US20080251821A1

    公开(公告)日：2008-10-16

    申请号：US11735226

    申请日：2007-04-13

    申请人： Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

    发明人： Chun-Yao Ko ,  Chung-Wei Chang ,  Han-Chi Liu ,  Shou-Gwo Wuu

    IPC分类号： H01L31/062 ,  H01L21/00

    CPC分类号： H01L27/14689 ,  H01L27/14609

    摘要： A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.

    摘要翻译： 制造图像传感器的方法包括提供具有像素区域和逻辑区域的半导体衬底，在像素区域中形成光感测元件，以及在像素区域中形成第一晶体管和在逻辑区域中形成第二晶体管。 在逻辑区域中的像素区域和第二晶体管中形成第一晶体管的步骤包括在像素区域和逻辑区域中执行第一注入处理，在像素区域和逻辑区域中执行第二注入处理，以及执行 仅在逻辑区域中进行第三次植入过程。

    Structure and method for single gate non-volatile memory device having a capacitor well doping design with improved coupling efficiency
    8.
    发明授权
    Structure and method for single gate non-volatile memory device having a capacitor well doping design with improved coupling efficiency 有权
    具有具有改善的耦合效率的具有电容器阱掺杂设计的单栅极非易失性存储器件的结构和方法

    公开(公告)号：US08890225B2

    公开(公告)日：2014-11-18

    申请号：US13273505

    申请日：2011-10-14

    申请人： Ta-Chuan Liao ,  Chien-Kao Yang ,  Ying-Kit Tsui ,  Shih-Hsien Chen ,  Liang-Tai Kuo ,  Chun-Yao Ko

    发明人： Ta-Chuan Liao ,  Chien-Kao Yang ,  Ying-Kit Tsui ,  Shih-Hsien Chen ,  Liang-Tai Kuo ,  Chun-Yao Ko

    IPC分类号： H01L21/108 ,  H01L21/336 ,  H01L29/788 ,  H01L27/115

    CPC分类号： H01L27/1156 ,  H01L21/265 ,  H01L21/28273 ,  H01L27/11558 ,  H01L28/60 ,  H01L29/788 ,  H01L29/7881

    摘要： The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.

    摘要翻译： NVM器件包括具有第一区域和第二区域的半导体衬底。 NVM装置包括形成在第一区域中的数据存储结构，并被设计成可操作地保持电荷。 NVM装置包括形成在第二区域中的电容器，并与用于数据操作的数据存储结构耦合。 数据存储结构包括在半导体衬底中的第一类型的第一掺杂阱。 数据存储结构包括第一掺杂阱上的第一栅介质特征。 数据存储结构包括设置在第一栅极电介质特征上并被配置为浮置的第一栅电极。 电容器包括第一类型的第二掺杂阱。 电容器包括第二掺杂阱上的第二栅极电介质特征。 电容器还包括设置在第二栅极电介质特征上并连接到第一栅电极的第二栅电极。