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    Direct determination of interface traps in MOS devices
    6.
    发明授权
    Direct determination of interface traps in MOS devices 有权
    直接确定MOS器件中的接口陷阱

    公开(公告)号：US06746883B2

    公开(公告)日：2004-06-08

    申请号：US10064036

    申请日：2002-06-04

    申请人： Steve S. Chung ,  Shang-Jr Chen ,  Chien-Kuo Yang ,  Der-Yuan Wu

    发明人： Steve S. Chung ,  Shang-Jr Chen ,  Chien-Kuo Yang ,  Der-Yuan Wu

    IPC分类号： H01L2166

    CPC分类号： G01R31/2621 ,  G01R31/2648 ,  G01R31/2831

    摘要： A low leakage charge pumping (CP) method has been implemented for direct determination of interface traps in ultra-short gate length MOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12 Å-16 Å gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has been demonstrated successfully for variousRTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. It can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relation to the interface trap generation. In addition, the current method can be used to determine the physical channel length of CMOS devices.

    摘要翻译： 已经实现了低泄漏电荷泵浦（CP）方法，用于在直接隧道状态下用超薄栅极氧化物直接确定超短栅极长度MOS器件中的界面陷阱。 可以从测量的CP电流中去除12Å-16Å栅极氧化物中的漏电流，从而可以准确测定界面陷阱。 已经成功地证明了这种方法成功地用于具有非常薄的栅极氧化物的各种RTNO生长和RPN处理的氧化物CMOS器件。 它可以用作超薄栅极氧化过程的良好监测器，以及与界面阱生成相关的器件可靠性的评估。 另外，目前的方法可以用来确定CMOS器件的物理通道长度。

    Method for producing a high-voltage and low-voltage MOS transistor with salicide structure
    7.
    发明授权
    Method for producing a high-voltage and low-voltage MOS transistor with salicide structure 有权
    用于生产具有自对准硅结构的高压和低压MOS晶体管的方法

    公开(公告)号：US06204129B1

    公开(公告)日：2001-03-20

    申请号：US09425606

    申请日：1999-10-22

    申请人： Ching-Chun Hwang ,  Wei-Chung Chen ,  Chien-Kuo Yang

    发明人： Ching-Chun Hwang ,  Wei-Chung Chen ,  Chien-Kuo Yang

    IPC分类号： H01L218234

    CPC分类号： H01L21/823456 ,  H01L21/823418 ,  H01L21/823443

    摘要： A method for producing self-aligned silicidation, substantially facilitating the integration of the high-voltage and low-voltage MOS device, is disclosed. The method includes providing, the present invention provides a integration of high-voltage and low-voltage MOS transistor, which self-aligned silicidation process. A substrate is provided incorporating a device, wherein the device is defined high-voltage MOS region and low-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxide is spaced from another of the field oxide by a MOS region. Moreover, a polysilicon layer is formed over said high-voltage MOS region and low-voltage MOS region, and a first dielectric layer is deposited above the polysilicon layer of the high-voltage MOS region and low-voltage MOS region. Consequently, a first photoresist layer is formed over the first dielectric layer, wherein defining and etching the first photoresist layer to form gates of high-voltage MOS and low-voltage MOS. Then, using said second photoresist layer as a mask above low-voltage MOS region, firstly implanting the substrate of the high-voltage MOS region to form conductivity-type grade therein, and then the second photoresist layer of low-voltage MOS region is removed. Moreover, spacers are formed on sidewall of said gates of high-voltage MOS and low-voltage MOS, and then a second dielectric layer is formed on the substrate of high-voltage and low-voltage MOS.

    摘要翻译： 公开了一种用于生产自对准硅化物的方法，其基本上便于高压和低压MOS器件的集成。 该方法包括提供本发明提供的高压和低压MOS晶体管的集成，其自对准硅化工艺。 提供了一种结合有器件的衬底，其中器件被限定为高电压MOS区和低电压MOS区。 接下来，在衬底上形成多个场氧化物，场氧化物中的一个与场氧化物中的另一个与MOS区隔开。 此外，在所述高压MOS区域和低电压MOS区域上形成多晶硅层，并且在高压MOS区域和低电压MOS区域的多晶硅层上方淀积第一电介质层。 因此，在第一介电层上形成第一光致抗蚀剂层，其中限定和蚀刻第一光致抗蚀剂层以形成高电压MOS和低电压MOS的栅极。 然后，使用所述第二光致抗蚀剂层作为低压MOS区域的掩模，首先将高压MOS区的基板注入其中形成导电型等级，然后除去低压MOS区的第二光致抗蚀剂层 。 此外，在高压MOS和低压MOS的所述栅极的侧壁上形成间隔物，然后在高电压和低电压MOS的衬底上形成第二电介质层。