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1.发明授权公开(公告)号：US08861300B2
公开(公告)日：2014-10-14
申请号：US12495418
申请日：2009-06-30
申请人： Chung Kuang Chin
发明人： Chung Kuang Chin
CPC分类号： G11C7/1006 , G11C7/1012 , G11C7/1075
摘要： A multi-port memory may be formed from a plurality of “simpler” memories. In one implementation, the memory includes a write port and a number of memories provided in groups, such that the write port supplies each of a plurality of copies of the data unit to a subset of the memories, each of the subset of memories being provided in a corresponding one of the groups, a number of the copies of the data unit being greater than two. Multiplexers may be implemented, each of which being associated with a corresponding one of the groups of the memories. One of the plurality of multiplexers may be configured to selectively supply one of the copies of the data unit from one of the memories. A read port may receive the one of the copies of the data unit from the one of the multiplexers and output the one of the copies of the data unit.
摘要翻译： 可以从多个“更简单”的存储器形成多端口存储器。 在一个实施方式中，存储器包括写入端口和分组中提供的多个存储器，使得写入端口将数据单元的多个拷贝中的每一个提供给存储器的子集，每个存储器子集被提供 在相应的一个组中，数据单元的副本数量大于2。 可以实现多路复用器，其中的每一个与存储器的组中的对应的一个相关联。 多个多路复用器之一可以被配置为从存储器中的一个选择性地提供数据单元的副本之一。 读取端口可以从多路复用器之一接收数据单元的副本之一，并输出数据单元的副本之一。
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公开(公告)号：US08370706B2
公开(公告)日：2013-02-05
申请号：US12572422
申请日：2009-10-02
CPC分类号： H03M13/2732 , H03M13/098 , H03M13/11 , H03M13/15 , H03M13/1515 , H03M13/19 , H03M13/271 , H03M13/6561 , H04L1/0041 , H04L1/0071
摘要： An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the codewords being generated by the ECC circuit based on input data and each of the codewords including error correction information and a portion of the data. The device may further include a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply data units in parallel, each of the data units including information from a corresponding one of the codewords; an interleaver circuit to receive the data units in parallel and output a second data units in parallel, each of the second data units including bits from different ones of the data units; and a number of output lines, each of which supplying a corresponding one of the second data units.
摘要翻译： 光学设备使用其中单个ECC码字通过多个光链路传输的交织技术来发送ECC码字。 在一个具体实现中，设备可以包括被配置成串联提供ECC码字的ECC电路，码字由ECC电路基于输入数据生成，并且每个码字包括纠错信息和数据的一部分。 该设备还可以包括串行到并行电路，其被配置为连续地接收每个码字，并且并行地提供数据单元，每个数据单元包括来自相应的一个码字的信息; 并行地接收数据单元并且并行地输出第二数据单元的交织器电路，每个第二数据单元包括来自不同数据单元的比特; 以及多个输出线，每个输出线提供相应的一个第二数据单元。
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公开(公告)号：US08848720B2
公开(公告)日：2014-09-30
申请号：US12732063
申请日：2010-03-25
IPC分类号： H04L29/06
CPC分类号： H04L43/0852
摘要： A propagation delay in the transmission of a frame from an initiator node to a peer node is determined by initially identifying a frame number and byte offset of a first incoming frame from the peer node at a time when the initiator node outputs a portion of a transmitted frame. The portion of the transmitted frame may be the first byte of a sub-frame within the transmitted frame. At the peer node, the frame number and byte offset of a second frame to be supplied to the initiator node is identified at a later time when the frame portion transmitted by the initiator node is received by the peer node, and such information is transmitted to the initiator node. Thus, since the frames output and received by the initiator node are typically of fixed duration, the frame number and byte offset of the incoming frame represent the time when the initiator node outputs the frame portion (a transmit time). In addition, the frame number and byte offset of the second frame represents the time at which the frame portion is received by the peer node (a receive time). Accordingly, by comparing the frame numbers and byte offsets of the first and second frames received from the peer node, a difference between transmit and receive times or propagation delay can be obtained.
摘要翻译： 通过在发起者节点输出发送的一部分的时间，首先识别来自对等节点的第一输入帧的帧号和字节偏移来确定帧从发起者节点传输到对等节点的传播延迟 帧。 发送帧的部分可以是发送帧内的子帧的第一个字节。 在对等节点，由发起方节点发送的帧部分由对端节点接收到的时候，识别要提供给发起方节点的第二帧的帧号和字节偏移，并将这些信息发送到 启动器节点。 因此，由于由发起者节点输出和接收的帧通常是固定持续时间，所以入局帧的帧号和字节偏移表示发起者节点输出帧部分的时间（发送时间）。 此外，第二帧的帧号和字节偏移表示对等节点接收帧部分的时间（接收时间）。 因此，通过比较从对等节点接收到的第一和第二帧的帧号和字节偏移，可以获得发射和接收时间之间的差异或传播延迟。
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公开(公告)号：US08775744B2
公开(公告)日：2014-07-08
申请号：US12550497
申请日：2009-08-31
CPC分类号： H04L49/9036
摘要： A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers.
摘要翻译： 描述了一种切换帧缓冲器，其中帧的时隙序列内的数据单元可以同时在切换帧缓冲器的端口输入和输出。 在一个实现中，写入端口可以在交换机的单个周期内接收数据单元。 可以提供多个存储器，其中存储器中的第一选定存储器构成存储器组，并且存储器中的第二选定存储器构成存储器子集，每个存储器组包括对应的一个存储器子集。 写入端口可以将数据单元的多个副本中的每一个提供给相应的一个存储器子集。 多路复用器可以与存储器组相关联，并且读取端口可以从不同的多路复用器接收多个数据单元的一个副本。
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公开(公告)号：US08300479B2
公开(公告)日：2012-10-30
申请号：US12731948
申请日：2010-03-25
申请人： Chung Kuang Chin , Edward E. Sprague , Prasad Paranjape , Swaroop Raghunatha , Venkat Talapaneni
发明人： Chung Kuang Chin , Edward E. Sprague , Prasad Paranjape , Swaroop Raghunatha , Venkat Talapaneni
CPC分类号： H04J3/0685 , H04J3/062
摘要： Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric. Since the timing of the output from the FIFOs is based on known system parameters, instead of the actual arrival of the slowest data unit group at its corresponding FIFO, time aligned data unit groups may be output regardless of whether the slowest data unit group is available.
摘要翻译： 与本公开一致，例如在交换机中提供多个FIFO缓冲器，交换机还包括交换结构。 基于在将数据单元组提供给其对应的FIFO的时间与参考时间之间的偏差或时间差，多个FIFO中的每一个被预先填充数据持续一段时间。 参考时间是时间，例如，在同步信号的前沿经过延迟时间之后，其定时是已知的系统参数，并且用于触发交换结构中的切换。 通常，延迟周期可以等于数据单元从诸如交换机或另一交换机的线路卡的输入电路传播到FIFO的等待时间（通常是另一个已知的系统参数）或时间长度 它接收数据单元。 在参考时间，可以从每个FIFO读取或输出时间对齐的数据单元组并提供给交换结构。 由于来自FIFO的输出的定时是基于已知的系统参数，而不是最慢的数据单元组在其对应的FIFO的实际到达，可以输出时间对齐的数据单元组，而不管最慢的数据单元组是否可用 。
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公开(公告)号：US20110235438A1
公开(公告)日：2011-09-29
申请号：US12731948
申请日：2010-03-25
申请人： Chung Kuang Chin , Edward E. Sprague , Prasad Paranjape , Swaroop Raghunatha , Venkat Talapaneni
发明人： Chung Kuang Chin , Edward E. Sprague , Prasad Paranjape , Swaroop Raghunatha , Venkat Talapaneni
CPC分类号： H04J3/0685 , H04J3/062
摘要： Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric. Since the timing of the output from the FIFOs is based on known system parameters, instead of the actual arrival of the slowest data unit group at its corresponding FIFO, time aligned data unit groups may be output regardless of whether the slowest data unit group is available.
摘要翻译： 与本公开一致，例如在交换机中提供多个FIFO缓冲器，交换机还包括交换结构。 基于在将数据单元组提供给其对应的FIFO的时间与参考时间之间的偏差或时间差，多个FIFO中的每一个被预先填充数据持续一段时间。 参考时间是时间，例如，在同步信号的前沿经过延迟时间之后，其定时是已知的系统参数，并且用于触发交换结构中的切换。 通常，延迟周期可以等于数据单元从诸如交换机或另一交换机的线路卡的输入电路传播到FIFO的等待时间（通常是另一个已知的系统参数）或时间长度 它接收数据单元。 在参考时间，可以从每个FIFO读取或输出时间对齐的数据单元组并提供给交换结构。 由于来自FIFO的输出的定时是基于已知的系统参数，而不是最慢的数据单元组在其对应的FIFO的实际到达，可以输出时间对齐的数据单元组，而不管最慢的数据单元组是否可用 。
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公开(公告)号：US20110055491A1
公开(公告)日：2011-03-03
申请号：US12550497
申请日：2009-08-31
IPC分类号： G06F12/00
CPC分类号： H04L49/9036
摘要： A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers.
摘要翻译： 描述了一种切换帧缓冲器，其中帧的时隙序列内的数据单元可以同时在切换帧缓冲器的端口输入和输出。 在一个实现中，写入端口可以在交换机的单个周期内接收数据单元。 可以提供多个存储器，其中存储器中的第一选定存储器构成存储器组，并且存储器中的第二选定存储器构成存储器子集，每个存储器组包括对应的一个存储器子集。 写入端口可以将数据单元的多个副本中的每一个提供给相应的一个存储器子集。 多路复用器可以与存储器组相关联，并且读取端口可以从不同的多路复用器接收多个数据单元的一个副本。
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公开(公告)号：US20110083051A1
公开(公告)日：2011-04-07
申请号：US12572422
申请日：2009-10-02
CPC分类号： H03M13/2732 , H03M13/098 , H03M13/11 , H03M13/15 , H03M13/1515 , H03M13/19 , H03M13/271 , H03M13/6561 , H04L1/0041 , H04L1/0071
摘要： An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the codewords being generated by the ECC circuit based on input data and each of the codewords including error correction information and a portion of the data. The device may further include a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply data units in parallel, each of the data units including information from a corresponding one of the codewords; an interleaver circuit to receive the data units in parallel and output a second data units in parallel, each of the second data units including bits from different ones of the data units; and a number of output lines, each of which supplying a corresponding one of the second data units.
摘要翻译： 光学设备使用其中单个ECC码字通过多个光链路传输的交织技术来发送ECC码字。 在一个具体实现中，设备可以包括被配置成串联提供ECC码字的ECC电路，码字由ECC电路基于输入数据生成，并且每个码字包括纠错信息和数据的一部分。 该设备还可以包括串行到并行电路，其被配置为连续地接收每个码字，并且并行地提供数据单元，每个数据单元包括来自相应的一个码字的信息; 并行地接收数据单元并且并行地输出第二数据单元的交织器电路，每个第二数据单元包括来自不同数据单元的比特; 以及多个输出线，每个输出线提供相应的一个第二数据单元。
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公开(公告)号：US20100328116A1
公开(公告)日：2010-12-30
申请号：US12495482
申请日：2009-06-30
申请人： Chung Kuang Chin , Prasad Paranjape
发明人： Chung Kuang Chin , Prasad Paranjape
IPC分类号： H03M9/00
摘要： Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams.
摘要翻译： 串行到并行和并行到串行转换设备可以提供将串行比特流有效转换成并行数据单元（反之亦然）。 在一个实现中，设备可以包括延迟电路，每个延迟电路被配置成接收串行数据流。 旋转电路可以接收延迟的串行数据流并重新排列串行数据流中的位。 寄存器电路可以接收转子电路的输出并且并行地并行地输出串行位流之一的多个位。
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10.发明授权公开(公告)号：US07768512B1
公开(公告)日：2010-08-03
申请号：US09371972
申请日：1999-08-10
摘要： A system and method for rendering a graphic primitive by linear or perspective interpolation from vertex points. An interpolation engine is employed to interpolate channel values along edges of the primitive to determine values along a scan line containing a selected point. The interpolation engine is then employed to interpolate along the scan line. Processing time may further be reduced by the use of an improved adder/subtractor as a component of the interpolation engine to reduce sequential steps and improve parallelism.
摘要翻译： 一种通过线性或透视插值从顶点渲染图形原语的系统和方法。 采用内插引擎来沿着图元边沿内插通道值，以确定沿着包含选定点的扫描线的值。 然后使用内插引擎沿着扫描线内插。 通过使用改进的加法器/减法器作为内插引擎的组件来进一步减少处理时间，以减少顺序步骤并提高并行性。
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