公开(公告)号：US09634862B2

公开(公告)日：2017-04-25

申请号：US14446958

申请日：2014-07-30

申请人： Coke S Reed ,  David Murphy

发明人： Coke S Reed ,  David Murphy

IPC分类号： H04L12/28 ,  H04L12/437

CPC分类号： H04L49/1523 ,  H04L12/437 ,  H04L45/74

摘要： An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

公开(公告)号：US20150023367A1

公开(公告)日：2015-01-22

申请号：US13072612

申请日：2011-03-25

申请人： Coke S. Reed ,  David Murphy

发明人： Coke S. Reed ,  David Murphy

IPC分类号： H04L12/937 ,  H04L12/933

CPC分类号： H04L49/254 ,  H04L45/583 ,  H04L45/60 ,  H04L49/15

摘要： An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

摘要翻译： 互连设备即使在高时钟速率，带宽增加和延迟较低的情况下也能实现改进的信号完整性。 互连装置可以包括多个逻辑单元和多个总线，所述多个逻辑单元以布置在包括逻辑单元LA，LC和LD的三元组的逻辑单元的选定配置中耦合所述多个逻辑单元。 逻辑单元LA和LC被定位成将数据发送到逻辑单元LD。 逻辑单元LC优先于逻辑单元LA以将数据发送到逻辑单元LD。 对于被划分为子分组的分组PKT，在逻辑单元LA处的分组PKT的分组以及指定目标的分组：（A）逻辑单元LC将分组PKT的子分组发送到逻辑单元LD和逻辑 单元LA不将分组PKT的子分组发送到逻辑单元LD; （B）逻辑单元LC不将数据分组发送到逻辑单元LD，逻辑单元LA将分组PKT的子分组发送到逻辑单元LD; 或者（C）逻辑单元LC不将数据分组发送到逻辑单元LD，逻辑单元LA不向分组PKT发送分组到逻辑单元LD。

公开(公告)号：US09479458B2

公开(公告)日：2016-10-25

申请号：US13072612

申请日：2011-03-25

申请人： Coke S. Reed ,  David Murphy

发明人： Coke S. Reed ,  David Murphy

IPC分类号： H04L12/28 ,  H04L12/937 ,  H04L12/933 ,  H04L12/775 ,  H04L12/773

CPC分类号： H04L49/254 ,  H04L45/583 ,  H04L45/60 ,  H04L49/15

摘要： An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD.

摘要翻译： 互连设备即使在高时钟速率，带宽增加和延迟较低的情况下也能实现改进的信号完整性。 互连装置可以包括多个逻辑单元和多个总线，所述多个逻辑单元以布置在包括逻辑单元LA，LC和LD的三元组的逻辑单元的选定配置中耦合所述多个逻辑单元。 逻辑单元LA和LC被定位成将数据发送到逻辑单元LD。 逻辑单元LC优先于逻辑单元LA以将数据发送到逻辑单元LD。 对于被划分为子分组的分组PKT，在逻辑单元LA处的分组PKT的分组以及指定目标的分组：（A）逻辑单元LC将分组PKT的子分组发送到逻辑单元LD和逻辑 单元LA不将分组PKT的子分组发送到逻辑单元LD; （B）逻辑单元LC不将数据分组发送到逻辑单元LD，逻辑单元LA将分组PKT的子分组发送到逻辑单元LD; 或者（C）逻辑单元LC不将数据分组发送到逻辑单元LD，逻辑单元LA不向分组PKT发送分组到逻辑单元LD。

公开(公告)号：US08825896B2

公开(公告)日：2014-09-02

申请号：US10866461

申请日：2004-06-10

申请人： Coke S. Reed ,  David Murphy

发明人： Coke S. Reed ,  David Murphy

IPC分类号： G06F15/173 ,  H04L12/56 ,  H04L29/08

CPC分类号： H04L45/00 ,  H04L45/742 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/201 ,  H04L49/3009 ,  H04L67/12

摘要： In a system, a memory controller separates a memory into multiple banks and enables a plurality of selected banks to be accessed concurrently. The memory controller further comprises a logic that creates a representation of a tree structure in memory and builds routing tables accessed by pointers at nodes in the tree memory structure, and a logic that finds a target memory address based on a received Internet Protocol (IP) address used by the tree memory structure and the routing table.

摘要翻译： 在系统中，存储器控制器将存储器分离成多个存储体，并且使多个所选择的存储体能够同时访问。 存储器控制器还包括在存储器中创建树结构的表示并构建通过树存储器结构中的节点处的指针访问的路由表的逻辑，以及基于接收到的因特网协议（IP）查找目标存储器地址的逻辑， 树存储器结构和路由表使用的地址。

公开(公告)号：US20090070487A1

公开(公告)日：2009-03-12

申请号：US12206598

申请日：2008-09-08

申请人： Coke S. Reed

发明人： Coke S. Reed

IPC分类号： G06F15/173

CPC分类号： H04L49/3072 ,  H04L49/101 ,  H04L49/1515

摘要： A network device and associated operating methods interface to a network. A network interface comprises a plurality of registers that receive data from a plurality of data sending devices and arrange the received data into at least a target address field and a data field, and a plurality of spreader units coupled to the register plurality that forward the data based on logic internal to the spreader units and spread the data wherein structure characteristic to the data is removed. A plurality of switches is coupled to the spreader unit plurality and forwards the data based on the target address field.

摘要翻译： 网络设备和相关联的操作方法与网络的接口。 网络接口包括从多个数据发送装置接收数据的多个寄存器，并将接收到的数据排列成至少目标地址字段和数据字段，以及耦合到寄存器多个的多个扩展单元，用于转发数据 基于扩展器单元内部的逻辑，并扩展其中结构特征到数据的数据被去除的数据。 多个开关耦合到扩展单元多个，并且基于目标地址字段转发数据。

公开(公告)号：US10893003B2

公开(公告)日：2021-01-12

申请号：US16712055

申请日：2019-12-12

申请人： Coke S. Reed ,  David Murphy ,  Ronald R. Denny ,  Michael R. Ives ,  Reed Devany

发明人： Coke S. Reed ,  David Murphy ,  Ronald R. Denny ,  Michael R. Ives ,  Reed Devany

IPC分类号： H04L12/50 ,  H04L12/935 ,  H04L29/06 ,  H04L12/933 ,  H04L12/741

摘要： Embodiments of an interconnect apparatus enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch described herein and in the patents incorporated herein. The Data Vortex switch is on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array. Since the Data Vortex switches are not crossbar switches, there is no need to globally set and reset the Data Vortex switches as different groups of packets enter the switches. Mounting the Data Vortex switch on the same chip as the array of processing cores reduces the power required and reduces latency.

公开(公告)号：US20150188987A1

公开(公告)日：2015-07-02

申请号：US13297201

申请日：2011-11-15

申请人： COKE S. REED ,  RON DENNY ,  MICHAEL IVES ,  THAINE HOCK

发明人： COKE S. REED ,  RON DENNY ,  MICHAEL IVES ,  THAINE HOCK

IPC分类号： H04L29/08 ,  H04L12/24

CPC分类号： H04L67/10 ,  G06F15/17318 ,  G06F15/17393 ,  H04L41/04 ,  H04L49/9042 ,  H04L49/9094

摘要： Embodiments of a data handling apparatus can include a network interface controller configured to interface a processing node to a network. The network interface controller can include a network interface, a register interface, a processing node interface, and logic. The network interface can include lines coupled to the network for communicating data on the network. The register interface can include lines coupled to multiple registers. The processing node interface can include at least one line coupled to the processing node for communicating data with a local processor local to the processing node wherein the local processor can read data to and write data from the registers. The logic can receive packets including a header and a payload from the network and can insert the packets into the registers as indicated by the header.

摘要翻译： 数据处理装置的实施例可以包括被配置为将处理节点与网络接口的网络接口控制器。 网络接口控制器可以包括网络接口，寄存器接口，处理节点接口和逻辑。 网络接口可以包括耦合到网络的线路，用于在网络上传送数据。 寄存器接口可以包括耦合到多个寄存器的线。 处理节点接口可以包括耦合到处理节点的至少一个线路，用于与处理节点本地处理的本地处理器通信数据，其中本地处理器可以向寄存器读取数据和写入数据。 该逻辑可以从网络接收包括报头和有效载荷的分组，并且可以将报文插入到报头中指示的报文中。

公开(公告)号：US20120185614A1

公开(公告)日：2012-07-19

申请号：US13352161

申请日：2012-01-17

申请人： Coke S. Reed

发明人： Coke S. Reed

IPC分类号： G06F15/16

CPC分类号： G06F12/0806 ,  G06F12/0802 ,  G06F15/17356 ,  H04L49/90 ,  H04L49/9063

摘要： A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises a plurality of cache mirror registers coupled to the controller that receive data to be forwarded to the processor plurality. The controller is responsive to a request to receive data by transferring requested data directly to public memory without interrupting the processor, and by transferring requested data via at least one cache mirror register for a transfer to processor local cache, and to processor working registers.

摘要翻译： 网络设备包括控制器，其管理通过互连多个处理器的网络的数据流。 处理器的处理器多个包括分为专用本地存储器和公共本地存储器，本地高速缓存和工作寄存器的本地存储器。 网络设备还包括耦合到控制器的多个高速缓存镜寄存器，其接收将被转发到处理器多个的数据。 控制器响应于通过将所请求的数据直接传送到公共存储器而不中断处理器来接收数据的请求，并且通过经由至少一个缓存镜像寄存器传送所请求的数据以传送到处理器本地高速缓存以及处理器工作寄存器来响应该请求。

公开(公告)号：US08099521B2

公开(公告)日：2012-01-17

申请号：US11925546

申请日：2007-10-26

申请人： Coke S. Reed

发明人： Coke S. Reed

IPC分类号： G06F15/16 ,  G06F13/00

CPC分类号： G06F12/0806 ,  G06F12/0802 ,  G06F15/17356 ,  H04L49/90 ,  H04L49/9063

摘要： A network device comprises a controller that manages data flow through a network interconnecting a plurality of processors. The processors of the processor plurality comprise a local memory divided into a private local memory and a public local memory, a local cache, and working registers. The network device further comprises a plurality of cache mirror registers coupled to the controller that receive data to be forwarded to the processor plurality. The controller is responsive to a request to receive data by transferring requested data directly to public memory without interrupting the processor, and by transferring requested data via at least one cache mirror register for a transfer to processor local cache, and to processor working registers.

摘要翻译： 网络设备包括控制器，其管理通过互连多个处理器的网络的数据流。 处理器的处理器多个包括分为专用本地存储器和公共本地存储器，本地高速缓存和工作寄存器的本地存储器。 网络设备还包括耦合到控制器的多个高速缓存镜寄存器，其接收将被转发到处理器多个的数据。 控制器响应于通过将所请求的数据直接传送到公共存储器而不中断处理器来接收数据的请求，并且通过经由至少一个缓存镜像寄存器传送所请求的数据以传送到处理器本地高速缓存以及处理器工作寄存器来响应该请求。

公开(公告)号：US06272141B1

公开(公告)日：2001-08-07

申请号：US09397333

申请日：1999-09-14

申请人： Coke S. Reed

发明人： Coke S. Reed

IPC分类号： H04L1228

CPC分类号： G06F15/17393 ,  G06F15/17375 ,  G06F15/803 ,  H04L12/42 ,  H04L45/06

摘要： A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a “deflection” or “hot potato” system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components and improving speed performance of message communication.