利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

19 条记录 (耗时 0.018 秒)

    System and method for managing addresses in a computing system
    1.
    发明授权
    System and method for managing addresses in a computing system 有权
    用于管理计算系统中的地址的系统和方法

    公开(公告)号：US08037259B2

    公开(公告)日：2011-10-11

    申请号：US12155294

    申请日：2008-06-02

    申请人： William J. Leinberger ,  Bobby Jim Kowalski ,  Ronald R. Denny

    发明人： William J. Leinberger ,  Bobby Jim Kowalski ,  Ronald R. Denny

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1027

    摘要： A method for retrieving and managing addresses is provided. The steps may include of receiving, at a first buffer of m buffers, a request for an address; obtaining the address from a corresponding first register of the m registers; sending the address, received by said obtaining, to a destination; storing the address, received by the obtaining, in the first buffer; and clearing the contents of a second buffer of the m buffers, in response to any of said receiving, obtaining or storing, without clearing the contents of said first buffer, wherein m is a positive integer.

    摘要翻译： 提供了一种检索和管理地址的方法。 这些步骤可以包括在m个缓冲器的第一缓冲器处接收对地址的请求; 从m个寄存器的相应的第一个寄存器获取地址; 将通过所述获取接收到的地址发送到目的地; 将通过获取接收的地址存储在第一缓冲器中; 以及在不清除所述第一缓冲器的内容的情况下，响应于所述接收，获取或存储中的任何一个，清除m个缓冲器的第二缓冲器的内容，其中m是正整数。

    Method for forming laminated multiple substrates
    2.
    发明授权
    Method for forming laminated multiple substrates 有权
    层压多层基板的形成方法

    公开(公告)号：US08028403B2

    公开(公告)日：2011-10-04

    申请号：US12379156

    申请日：2009-02-13

    申请人： Deepak K. Pai ,  Ronald R. Denny

    发明人： Deepak K. Pai ,  Ronald R. Denny

    IPC分类号： H05K3/36 ,  B23K31/00

    CPC分类号： H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

    摘要： The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

    摘要翻译： 本发明提供了用于层叠和互连多个基板以形成多层封装或其他电路部件的多种技术。 可以在两个或更多个基板中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将两个或更多个基底压在一起以经由粘合剂膜机械地粘合两个或更多个基底。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

    Method and apparatus for adjusting the clock delay in systems with multiple integrated circuits
    3.
    发明授权
    Method and apparatus for adjusting the clock delay in systems with multiple integrated circuits 失效
    用于调整具有多个集成电路的系统中的时钟延迟的方法和装置

    公开(公告)号：US06621882B2

    公开(公告)日：2003-09-16

    申请号：US09798155

    申请日：2001-03-02

    申请人： Ronald R. Denny ,  Chris H. Simon ,  Joan E. Zak

    发明人： Ronald R. Denny ,  Chris H. Simon ,  Joan E. Zak

    IPC分类号： H04L700

    CPC分类号： G06F1/10 ,  H03L7/0812

    摘要： An apparatus and method for adjusting the clock delay in systems with multiple integrated circuits has a controller, a programmable clock generator and a plurality of integrated circuits, each integrated circuit including a data flip-flop, a programmable delay and a clock-fanout tree, wherein the clock delay in the integrated circuits is adjusted to match the inherent delay in the integrated circuit having the longest inherent delay.

    摘要翻译： 用于调整具有多个集成电路的系统中的时钟延迟的装置和方法具有控制器，可编程时钟发生器和多个集成电路，每个集成电路包括数据触发器，可编程延迟和时钟扇出树， 其中集成电路中的时钟延迟被调整以匹配具有最长固有延迟的集成电路中的固有延迟。

    Connector for orthogonally mounting circuit boards
    4.
    发明授权
    Connector for orthogonally mounting circuit boards 失效
    正交电路板连接器

    公开(公告)号：US4708660A

    公开(公告)日：1987-11-24

    申请号：US877311

    申请日：1986-06-23

    申请人： Richard J. Claeys ,  Ronald R. Denny ,  Joseph D. Vaughan ,  Charles Eumurian

    发明人： Richard J. Claeys ,  Ronald R. Denny ,  Joseph D. Vaughan ,  Charles Eumurian

    IPC分类号： H01R12/50 ,  H01R12/71 ,  H01R12/73 ,  H01R13/28 ,  H01R13/631 ,  H01R24/84 ,  H01R23/70

    CPC分类号： H01R13/28 ,  H01R24/84 ,  H01R12/716 ,  H01R12/73 ,  H01R13/631 ,  H01R13/645

    摘要： A connecting device is disclosed for electrically and mechanically linking multiple circuit boards arranged in two perpendicular stacks. The connecting device includes two identical connectors, each with a plurality of outwardly extended electrical socket contacts, and a pair of opposite, electrically insulative shoulders projected outwardly beyond the socket contacts. Electrical pin contacts are recessed into the shoulders. The pair of connectors can be engaged when in facing relation, with one of them rotated 90.degree. relative to the other. As the connectors are moved toward engagement, each shoulder of each connector enters into a nesting relation between the opposed shoulders of the other connector, pre-aligning the opposed pin and socket contacts. The shoulders have inclined edges at their outer faces, to assist in capturing their associated opposed shoulders and guide them, in a self-aligning manner, into the nesting relation. The connectors require a 90.degree. angular offset for their engagement, and thus facilitate interconnection of circuit boards in orthogonal stacks.

    摘要翻译： 公开了一种用于电气和机械连接以两个垂直堆叠布置的多个电路板的连接装置。 连接装置包括两个相同的连接器，每个连接器具有多个向外延伸的电插座触头，以及一对相对的电绝缘肩部，突出向外突出超过插座触点。 电引脚触点凹入肩部。 一对连接器可以面对关系时啮合，其中一个连接器相对于另一个旋转90度。 当连接器朝向接合方向移动时，每个连接器的每个肩部进入到另一个连接器的相对的肩部之间的嵌套关系，预先对准相对的销和插座触点。 肩部在其外表面具有倾斜的边缘，以协助捕获相关的相对的肩部并以自对准的方式引导它们进入嵌套关系。 连接器需要90°的角度偏移来进行接合，从而便于正交堆叠中电路板的互连。

    Technique for laminating multiple substrates
    7.
    发明授权
    Technique for laminating multiple substrates 有权
    复合多层基板的技术

    公开(公告)号：US07490402B2

    公开(公告)日：2009-02-17

    申请号：US11902758

    申请日：2007-09-25

    申请人： Deepak K. Pai ,  Ronald R. Denny

    发明人： Deepak K. Pai ,  Ronald R. Denny

    IPC分类号： H05K3/36 ,  B23K31/00

    CPC分类号： H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

    摘要： The present invention provides a number of techniques for laminating and interconnecting multiple substrates to form a multilayer package or other circuit component. A solder bump may be formed on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates then may be pressed together to mechanically bond the two or more substrates via the adhesive films. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

    摘要翻译： 本发明提供了用于层叠和互连多个基板以形成多层封装或其他电路部件的多种技术。 可以在两个或更多个基板中的至少一个的导电焊盘上形成焊料凸块。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 然后可以将两个或更多个基底压在一起以经由粘合剂膜机械地粘合两个或更多个基底。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。