利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

62 条记录 (耗时 0.037 秒)

    Use of redundant routes to increase the yield and reliability of a VLSI layout
    6.
    发明授权
    Use of redundant routes to increase the yield and reliability of a VLSI layout 有权
    使用冗余路由来提高VLSI布局的收益和可靠性

    公开(公告)号：US07308669B2

    公开(公告)日：2007-12-11

    申请号：US10908593

    申请日：2005-05-18

    申请人： Markus T. Buehler ,  John M. Cohn ,  David J. Hathaway ,  Jason D. Hibbeler ,  Juergen Koehl

    发明人： Markus T. Buehler ,  John M. Cohn ,  David J. Hathaway ,  Jason D. Hibbeler ,  Juergen Koehl

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5068

    摘要： Disclosed is a method and system for inserting redundant paths into an integrated circuit. Particularly, the invention provides a method for identifying a single via in a first path connecting two elements, determining if an alternate route is available for connecting the two elements (other than a redundant via), and for inserting a second path into the available alternate route. The combination of the first and second paths provides greater redundancy than inserting a redundant via alone. More importantly, such redundant paths provide for redundancy when congestion prevents a redundant via from being inserted adjacent to the single via. An embodiment of the method further comprises removing the single via and any redundant wire segments, if all of the additional vias used to form the second path can be made redundant.

    摘要翻译： 公开了一种将冗余路径插入到集成电路中的方法和系统。 特别地，本发明提供了一种用于在连接两个元件的第一路径中识别单个通孔的方法，确定替代路线是否可用于连接两个元件（不同于冗余通路），以及用于将第二路径插入到可用替代 路线。 第一和第二路径的组合提供了比单独插入冗余通道更大的冗余。 更重要的是，当拥塞阻止冗余通道被插入邻近单个通道时，这种冗余路径提供了冗余。 如果用于形成第二路径的所有附加通孔都可以是冗余的，则该方法的实施例还包括去除单个通孔和任何冗余线段。

    Object placement aid
    7.
    发明授权
    Object placement aid 失效
    对象放置辅助

    公开(公告)号：US5535134A

    公开(公告)日：1996-07-09

    申请号：US253898

    申请日：1994-06-03

    申请人： John M. Cohn ,  Fook-Luen Heng

    发明人： John M. Cohn ,  Fook-Luen Heng

    IPC分类号： H01L21/82 ,  G06F17/50

    CPC分类号： G06F17/509 ,  G06F17/5068 ,  G06F2217/06 ,  Y10S706/921

    摘要： An existing layout is modified to ensure compliance with design rules and any user-defined rules by deriving a horizontal constraint model and a vertical constraint model. For each of the vertical and horizontal orientations in turn, violations of the rules are identified. For each orientation in turn, the violations are removed in such a way that objects in the layout are moved the least amount necessary. A given object may also be inserted into an existing layout in such a way that perturbation of objects in the existing layout is minimized by exploring solutions allowing for object merger and non-merger solutions and choosing the best one based on predetermined criteria. Given a group of objects, a layout may also be created in such a way that successive objects are placed to minimize movement of objects already placed. Placement of an object in an existing layout may also be improved by removing the object and inserting it as if it were a new object a number of times until no further improvement is noted in its placement.

    摘要翻译： 修改现有布局以通过导出水平约束模型和垂直约束模型来确保符合设计规则和任何用户定义的规则。 依次对每个垂直和水平方向，都会识别违反规则的行为。 对于每个方向，依次删除违规行为，使布局中的对象移动到最少的必要数量。 给定对象也可以插入到现有布局中，使得通过探索允许对象合并和非合并解决方案并基于预定标准选择最佳对象的解决方案来最小化现有布局中的对象的扰动。 给定一组对象，也可以以这样的方式创建布局，使得连续的对象被放置以使已经放置的对象的移动最小化。 现有布局中的对象的放置也可以通过移除对象并将其插入多个对象来进行改进，直到在其布局中没有进一步改进。

    Method for IC wiring yield optimization, including wire widening during and after routing
    8.
    发明授权
    Method for IC wiring yield optimization, including wire widening during and after routing 有权
    IC布线产量优化方法，包括布线期间和之后的线宽

    公开(公告)号：US08230378B2

    公开(公告)日：2012-07-24

    申请号：US12572297

    申请日：2009-10-02

    申请人： John M. Cohn ,  Jason D. Hibbeler ,  Gustavo E. Tellez

    发明人： John M. Cohn ,  Jason D. Hibbeler ,  Gustavo E. Tellez

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

    摘要翻译： 公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。 该方法执行满足布线拥塞约束的初始全局路由。 接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。 之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。 使用关键区域产量模型进行布线后布线宽度和布线调整。 此外，该方法允许优化已经路由的数据。

    Pattern-matching for transistor level netlists
    9.
    发明授权
    Pattern-matching for transistor level netlists 失效
    晶体管级网表的模式匹配

    公开(公告)号：US06473881B1

    公开(公告)日：2002-10-29

    申请号：US09702313

    申请日：2000-10-31

    申请人： Valerie D. Lehner ,  John M. Cohn ,  Ulrich A. Finkler

    发明人： Valerie D. Lehner ,  John M. Cohn ,  Ulrich A. Finkler

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068

    摘要： A single pattern-matching algorithm which allows both exact and inexact pattern-matching so that transistor-level design automation tools can reliably perform timing analysis, electrical rules checking, noise analysis, test pattern generation, formal design verification, and the like prior to manufacturing custom logic. The user (circuit designer) specifies which of each of the pattern external nets may be matched inexactly (attached to Vdd, attached to GND, and shorted to other external nets), with the remainder of the pattern external net connections being matched using exact isomorphism constraints. The method described herein achieves a substantial reduction in the number of patterns which circuit designers must generate, and altogether eliminates the need for an exponential number of patterns by providing an inexact pattern matcher to circuit designers. It further provides rooted sub-graph isomorphism so that a user can query whether a particular pattern is embedded at a particular location in the main circuit design, utilizing inexact sub-graph isomorphism

    摘要翻译： 单一模式匹配算法，允许精确和不精确的模式匹配，以便晶体管级设计自动化工具可以在制造之前可靠地执行时序分析，电气规则检查，噪声分析，测试模式生成，正式设计验证等 定制逻辑。 用户（电路设计者）指定每个模式外部网络中的哪一个可以精确匹配（附加到Vdd，连接到GND，并与其他外部网络短接），其余模式外部网络连接使用精确同构 约束。 本文描述的方法实现了电路设计者必须生成的图案数量的显着减少，并且通过向电路设计者提供不精确的图案匹配器，完全不需要指数数目的图案。 它还提供了根系的子图同构，使得用户可以在主电路设计中的特定位置查询特定模式是否被嵌入，利用不精确的子图同构

    Method for IC wiring yield optimization, including wire widening during and after routing
    10.
    发明授权
    Method for IC wiring yield optimization, including wire widening during and after routing 失效
    IC布线产量优化方法，包括布线期间和之后的线宽

    公开(公告)号：US07657859B2

    公开(公告)日：2010-02-02

    申请号：US11275076

    申请日：2005-12-08

    申请人： John M. Cohn ,  Jason D. Hibbeler ,  Gustavo E. Tellez

    发明人： John M. Cohn ,  Jason D. Hibbeler ,  Gustavo E. Tellez

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： Disclosed are embodiments of a method, service, and computer program product for performing yield-aware IC routing for a design. The method performs an initial global routing which satisfies wiring congestion constraints. Next, the method performs wire spreading and wire widening on the global route, layer by layer, based on, for example, a quadratic congestion optimization. Following this, timing closure is performed on the global route using results of the wire spreading and wire widening. Post-routing wiring width and wire spreading adjustments are made using the critical area yield model. In addition, the method allows for the optimization of already-routed data.

    摘要翻译： 公开了用于为设计执行屈服感知IC路由的方法，服务和计算机程序产品的实施例。 该方法执行满足布线拥塞约束的初始全局路由。 接下来，该方法基于例如二次拥塞优化来逐层地在全局路由上执行线扩展和线拓宽。 之后，使用电线扩展和线宽加工的结果，在全局路线上执行定时关闭。 使用关键区域产量模型进行布线后布线宽度和布线调整。 此外，该方法允许优化已经路由的数据。