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23 条记录 (耗时 0.037 秒)

    Pattern-matching for transistor level netlists
    8.
    发明授权
    Pattern-matching for transistor level netlists 失效
    晶体管级网表的模式匹配

    公开(公告)号：US06473881B1

    公开(公告)日：2002-10-29

    申请号：US09702313

    申请日：2000-10-31

    申请人： Valerie D. Lehner ,  John M. Cohn ,  Ulrich A. Finkler

    发明人： Valerie D. Lehner ,  John M. Cohn ,  Ulrich A. Finkler

    IPC分类号： G06F1750

    CPC分类号： G06F17/5068

    摘要： A single pattern-matching algorithm which allows both exact and inexact pattern-matching so that transistor-level design automation tools can reliably perform timing analysis, electrical rules checking, noise analysis, test pattern generation, formal design verification, and the like prior to manufacturing custom logic. The user (circuit designer) specifies which of each of the pattern external nets may be matched inexactly (attached to Vdd, attached to GND, and shorted to other external nets), with the remainder of the pattern external net connections being matched using exact isomorphism constraints. The method described herein achieves a substantial reduction in the number of patterns which circuit designers must generate, and altogether eliminates the need for an exponential number of patterns by providing an inexact pattern matcher to circuit designers. It further provides rooted sub-graph isomorphism so that a user can query whether a particular pattern is embedded at a particular location in the main circuit design, utilizing inexact sub-graph isomorphism

    摘要翻译： 单一模式匹配算法，允许精确和不精确的模式匹配，以便晶体管级设计自动化工具可以在制造之前可靠地执行时序分析，电气规则检查，噪声分析，测试模式生成，正式设计验证等 定制逻辑。 用户（电路设计者）指定每个模式外部网络中的哪一个可以精确匹配（附加到Vdd，连接到GND，并与其他外部网络短接），其余模式外部网络连接使用精确同构 约束。 本文描述的方法实现了电路设计者必须生成的图案数量的显着减少，并且通过向电路设计者提供不精确的图案匹配器，完全不需要指数数目的图案。 它还提供了根系的子图同构，使得用户可以在主电路设计中的特定位置查询特定模式是否被嵌入，利用不精确的子图同构

    Common memory programming
    9.
    发明授权
    Common memory programming 有权
    常用内存编程

    公开(公告)号：US08438341B2

    公开(公告)日：2013-05-07

    申请号：US12816588

    申请日：2010-06-16

    申请人： Ulrich A. Finkler ,  Steven N. Hirsch ,  Harold E. Reindel

    发明人： Ulrich A. Finkler ,  Steven N. Hirsch ,  Harold E. Reindel

    IPC分类号： G06F12/00

    CPC分类号： G06F9/544

    摘要： A method for unidirectional communication between tasks includes providing a first task having access to an amount of virtual memory, blocking a communication channel portion of said first task's virtual memory, such that the first task cannot access said portion, providing a second task, having access to an amount of virtual memory equivalent to the first task's virtual memory, wherein a communication channel portion of the second task's virtual memory corresponding to the blocked portion of the first task's virtual memory is marked as writable, transferring the communication channel memory of the second task to the first task, and unblocking the communication channel memory of the first task.

    摘要翻译： 一种用于任务之间的单向通信的方法包括提供具有对一定量的虚拟存储器的访问的第一任务，阻止所述第一任务的虚拟存储器的通信信道部分，使得第一任务不能访问所述部分，提供第二任务， 涉及与第一任务的虚拟存储器相当的虚拟存储器的量，其中与第一任务的虚拟存储器的被阻止部分相对应的第二任务的虚拟存储器的通信信道部分被标记为可写，传送第二任务的通信信道存储器 到第一个任务，并解除第一个任务的通信通道存储器。

    Parallel intrusion search in hierarchical VLSI designs with substituting scan line
    10.
    发明授权
    Parallel intrusion search in hierarchical VLSI designs with substituting scan line 有权
    在具有替代扫描线的分层VLSI设计中的并行入侵搜索

    公开(公告)号：US08006207B2

    公开(公告)日：2011-08-23

    申请号：US12198172

    申请日：2008-08-26

    申请人： Ulrich A. Finkler

    发明人： Ulrich A. Finkler

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： Mechanisms are provided for performing intrusion searching of a hierarchical integrated circuit design. These mechanisms may receive the hierarchical integrated circuit design and perform a parallel intrusion search operation, that utilizes a substituting scan line, on the hierarchical integrated circuit design to identify intrusions of geometric objects in the hierarchical integrated circuit design. The mechanisms may further record intrusions of geometric objects in the hierarchical integrated circuit design identified by the parallel intrusion search operation. The parallel intrusion search operation may utilize a plurality of separate intrusion searches executed by the data processing system in parallel on the hierarchical integrated circuit design.

    摘要翻译： 提供了用于执行分级集成电路设计的入侵搜索的机制。 这些机制可以接收分级集成电路设计，并且在分层集成电路设计中执行使用替代扫描线的并行入侵搜索操作来识别分层集成电路设计中的几何对象的入侵。 这些机制可以进一步记录通过并行入侵搜索操作识别的分层集成电路设计中的几何对象的入侵。 并行入侵搜索操作可以在分层集成电路设计上并行地利用由数据处理系统执行的多个单独的入侵搜索。