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    Patient movement detection system and method
    1.
    发明申请
    Patient movement detection system and method 有权
    患者运动检测系统及方法

    公开(公告)号：US20100298742A1

    公开(公告)日：2010-11-25

    申请号：US12730663

    申请日：2010-03-24

    Applicant: David Perlman ,  Joseph Himle

    Inventor： David Perlman ,  Joseph Himle

    IPC: A61B5/103

    CPC classification number: G16H40/63 ,  A61B5/1116 ,  A61B5/447 ,  A61B5/6801 ,  A61B5/7275 ,  A61B5/742 ,  A61B5/746 ,  A61B2560/0443 ,  A61B2562/0219 ,  A61B2562/18 ,  G06F19/00

    Abstract: A monitoring system and method tracks a patient's position over time and ensures that proper turning or other manipulation is done within the time prescribed. Preferably, the techniques herein continuously monitor patient position and alert medical or other personnel of the need for turning or other patient manipulation. The system may be implemented within a medical or other care facility, or within a patient's home.

    Abstract translation: 监测系统和方法随着时间跟踪病人的位置，并确保在规定的时间内进行适当的转动或其他操纵。 优选地，本文的技术连续地监视患者位置并且向医疗或其他人员通知需要转动或其他患者操纵。 该系统可以在医疗或其他护理设施内或在患者的家中实现。

    High reliability memory module with a fault tolerant address and command bus
    3.
    发明申请
    High reliability memory module with a fault tolerant address and command bus 有权
    高可靠性存储器模块，具有容错地址和命令总线

    公开(公告)号：US20060236201A1

    公开(公告)日：2006-10-19

    申请号：US11406669

    申请日：2006-04-20

    Applicant: Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    Inventor： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    IPC: H03M13/00

    CPC classification number: H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

    Abstract translation: 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和 具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行 接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。 通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。 存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。 模块上的冗余联系人可防止出现单点故障。

    HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS
    4.
    发明申请
    HIGH RELIABILITY MEMORY MODULE WITH A FAULT TOLERANT ADDRESS AND COMMAND BUS 有权

    公开(公告)号：US20070204201A1

    公开(公告)日：2007-08-30

    申请号：US11741319

    申请日：2007-04-27

    Applicant: Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    Inventor： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    IPC: G11C29/00

    CPC classification number: H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

    PORTABLE URINAL FOR USE WITH PATIENTS WITH LIMITED MOBILITY
    5.
    发明公开
    PORTABLE URINAL FOR USE WITH PATIENTS WITH LIMITED MOBILITY 审中-公开

    公开(公告)号：US20240164597A1

    公开(公告)日：2024-05-23

    申请号：US18514552

    申请日：2023-11-20

    Applicant: David Perlman

    Inventor： David Perlman

    IPC: A47K11/12 ,  A47K11/02

    CPC classification number: A47K11/12 ,  A47K11/02

    Abstract: A portable urinal for use by people having limited mobility is disclosed. The portable urinal comprising a cabinet and a vessel. The cabinet having a base, a top wall, a rear wall, an openable and closeable door offset from the rear wall, and sidewalls extending from the base to the top wall and between the rear wall and the door. The vessel is located within the cabinet, and the vessel is configured to receive urine from a user. In addition, the vessel is removeable from the cabinet to facilitate disposal of the urine within the vessel.

    Awareness enhancement and monitoring devices for the treatment of certain impulse control disorders
    6.
    发明申请
    Awareness enhancement and monitoring devices for the treatment of certain impulse control disorders 审中-公开
    意识提高和监测装置用于治疗某些冲动控制障碍

    公开(公告)号：US20070080812A1

    公开(公告)日：2007-04-12

    申请号：US11233972

    申请日：2005-09-23

    Applicant: David Perlman

    Inventor： David Perlman

    IPC: G08B23/00

    CPC classification number: A61B5/165 ,  A61B5/1114 ,  A61B5/1127 ,  A61B5/16 ,  A61B5/486 ,  A61B5/6805 ,  A61B5/681 ,  A61B5/6822 ,  A61B5/6826 ,  A61B5/6838

    Abstract: Apparatus for monitoring and discouraging trichotillomania and other unwanted behaviors includes a proximity detector, an event logger, and a user input facilitating event characterization. The proximity detector includes a sensor and an element associated with the arm, hand, finger, head or other user body part. The proximity detector is operative to generate an output signal in the event that the element has physically moved to within a predetermined distance relative to the sensor. The apparatus further includes a device operative to alert the user in response to the output signal generated by the proximity detector. Additional circuitry is provided enabling events to be examined and reviewed. Such circuitry would include a memory for storing information associated with alert events and an interface allowing the events to be examined and reviewed on a personal computer, for example. The provision of a real-time clock further enables date or time information to be stored in conjunction with an event. For additional insight into the events, an input may be provided allowing a user to characterize an event at the time of occurrence.

    Abstract translation: 用于监测和阻止拔毛病和其他不需要的行为的装置包括接近检测器，事件记录器和促进事件表征的用户输入。 接近检测器包括传感器和与手臂，手指，手指，头部或其他使用者主体部分相关联的元件。 接近检测器可操作以在元件物理移动到相对于传感器预定距离内的情况下产生输出信号。 该装置还包括可响应于由接近检测器产生的输出信号来警告用户的装置。 提供附加电路，使事件能够被检查和审查。 这种电路将包括用于存储与警报事件相关联的信息的存储器和允许在个人计算机上检查和审查事件的接口。 提供实时时钟进一步使日期或时间信息与事件结合存储。 为了进一步了解事件，可以提供允许用户在发生时表征事件的输入。

    High reliability memory module with a fault tolerant address and command bus
    7.
    发明申请
    High reliability memory module with a fault tolerant address and command bus 有权

    公开(公告)号：US20060190780A1

    公开(公告)日：2006-08-24

    申请号：US11406717

    申请日：2006-04-20

    Applicant: Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    Inventor： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    IPC: G11C29/00

    CPC classification number: H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

    Biofeedback device for treating obsessive compulsive spectrum disorders (OCSDs)
    8.
    发明授权
    Biofeedback device for treating obsessive compulsive spectrum disorders (OCSDs) 失效
    用于治疗强迫性强迫症（OCSD）的生物反馈装置

    公开(公告)号：US06762687B2

    公开(公告)日：2004-07-13

    申请号：US10175934

    申请日：2002-06-20

    Applicant: David Perlman

    Inventor： David Perlman

    IPC: G08B2300

    CPC classification number: G08B23/00

    Abstract: A biofeedback device for treatment of certain obsessive compulsive spectrum and habit disorders including trichotillomania (hair pulling), onychophagia (nail biting), thumb-sucking, skin-scratching (dermatillomania) and certain other self-inflicted harm, includes a sensing element and triggering device, both worn on various parts of the body, depending upon the particular characteristics of an individual's disorder. The biofeedback device is able to sense the movement of one body part relative to another and set off an alarm mechanism prior to contact, assisting the patient in avoiding the destructive behavior.

    Abstract translation: 用于治疗某些强迫性强迫症和习惯障碍（包括拔毛症），精神病（指甲咬伤），拇指吸吮，皮肤搔痒（皮肤搔痒症）和某些其他自身伤害的生物反馈装置包括感测元件和触发 装置，均佩戴在身体的各个部位上，这取决于个体病症的特征。 生物反馈装置能够感测一个身体部分相对于另一个身体部分的运动，并在接触之前发出报警机构，从而帮助患者避免破坏行为。

    High reliability memory module with a fault tolerant address and command bus
    10.
    发明申请
    High reliability memory module with a fault tolerant address and command bus 有权
    高可靠性存储器模块，具有容错地址和命令总线

    公开(公告)号：US20070250756A1

    公开(公告)日：2007-10-25

    申请号：US11406718

    申请日：2006-04-20

    Applicant: Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    Inventor： Kevin Gower ,  Bruce Hazelzet ,  Mark Kellogg ,  David Perlman

    IPC: G11C29/00

    CPC classification number: H05K1/117 ,  G06F11/1044 ,  G11C5/04 ,  G11C2029/0409 ,  H05K2201/09145 ,  H05K2203/167

    Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

    Abstract translation: 具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。 存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和 具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行 接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。 通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。 存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。 模块上的冗余联系人可防止出现单点故障。

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