公开(公告)号：US08570109B2

公开(公告)日：2013-10-29

申请号：US13081119

申请日：2011-04-06

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： H03K3/03

CPC分类号： H03K3/0322 ,  H03K23/542

摘要： A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

摘要翻译： 一种环形振荡器，包括多个缓冲单元，每个缓冲单元具有交叉耦合结构，用于使用施加有预定电压电平的偏置电压来产生时钟信号，其中时钟信号具有对应于偏置电压的摆幅宽度。

公开(公告)号：US07812650B2

公开(公告)日：2010-10-12

申请号：US12157235

申请日：2008-06-09

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： H03L7/06

CPC分类号： H03L7/0893 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06

摘要： Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

摘要翻译： 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。

公开(公告)号：US07791391B2

公开(公告)日：2010-09-07

申请号：US12215829

申请日：2008-06-30

申请人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K5/13

CPC分类号： H03L7/0814 ,  H03K2005/00286 ,  H03L7/087

摘要： A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out, N-bit code values are stored according to a plurality of detected phase differences. A controller shares the N-bit code counter, controls the generation of the N-bit code values according to the plurality of detected phase differences, and controls the storing of the N-bit code values in an allocated space of the storage by use of a multiplexer configured to provide the plurality of detected phase differences to the N-bit code counter, and a demultiplexer configured to store the N-bit code values in the allocated space of the storage.

摘要翻译： 正交相位校正电路包括N比特码计数器，被配置为当执行正交相位校正时根据检测到的相位差产生N比特码值，根据多个检测相位存储N比特码值 差异 A控制器共享N位代码计数器，根据多个检测到的相位差控制N位代码值的产生，并且通过使用N位代码值来存储N位代码值到存储器的分配空间中 多路复用器，被配置为向N位代码计数器提供多个检测到的相位差，以及解复用器，被配置为将N位代码值存储在存储器的分配空间中。

公开(公告)号：US20090160510A1

公开(公告)日：2009-06-25

申请号：US12157235

申请日：2008-06-09

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： H03L7/06 ,  H03K3/01

CPC分类号： H03L7/0893 ,  H03L7/099 ,  H03L7/107 ,  H03L2207/06

摘要： Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.

摘要翻译： 偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元 以接收放大单元的输出信号以输出偏置电压。

公开(公告)号：US20090115467A1

公开(公告)日：2009-05-07

申请号：US12005515

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03B19/00 ,  G06F1/06

CPC分类号： G06F1/06

摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

摘要翻译： 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

公开(公告)号：US20090115459A1

公开(公告)日：2009-05-07

申请号：US12005564

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/017 ,  H03K5/125

CPC分类号： H03K5/1565

摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal.

摘要翻译： 一种半导体器件，包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于一个或多个脉冲信号输出多个脉冲信号中的一个作为使能信号 半导体器件的工作频率以及响应于使能信号检测外部时钟信号的占空比的占空比检测单元。

公开(公告)号：US20090058482A1

公开(公告)日：2009-03-05

申请号：US12005923

申请日：2007-12-28

申请人： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Jun-Woo Lee ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/017

CPC分类号： H03K5/1534 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565

摘要： Semiconductor memory device with duty correction circuit includes a clock edge detector configured to generate first and second detection pulses in response to a transition timing of a common clock signal in an initial measurement operation; a duty detector configured to compare the first and second detection pulses to output comparison result signals; and a code counter configured to control the duty detector based on the comparison signals outputted from the duty detector in the initial measurement operation.

公开(公告)号：US08283962B2

公开(公告)日：2012-10-09

申请号：US12005515

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/00

CPC分类号： G06F1/06

摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.

摘要翻译： 半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有 低频和不同的激活时序具有恒定的相位差。

公开(公告)号：US07863955B2

公开(公告)日：2011-01-04

申请号：US12005564

申请日：2007-12-27

申请人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Kyung-Hoon Kim ,  Dae-Kun Yoon ,  Taek-Sang Song

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.

摘要翻译： 一种半导体器件包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于频率输出多个脉冲信号中的一个作为使能信号 以及占空比检测单元，用于响应于使能信号检测外部时钟信号的占空比。

公开(公告)号：US07839196B2

公开(公告)日：2010-11-23

申请号：US12342778

申请日：2008-12-23

申请人： Dae Kun Yoon

发明人： Dae Kun Yoon

IPC分类号： H03K5/13

CPC分类号： H03K5/15013 ,  H03K5/13 ,  H03K5/1565 ,  H03K2005/00052

摘要： A multi-phase clock generation circuit having a low skew imprecision is presented. The circuit includes a phase clock generation block and a phase correction block. The phase clock generation block is configured to generate a plurality of phase clocks having phases different from each other with response to a pair of input clocks. The phase correction block is configured to generate final output interpolated phase clocks in which each has a center phase by adjusted by multiple phase clocks that have adjacent phases.

摘要翻译： 提出了具有低偏移不精确度的多相时钟产生电路。 该电路包括相位时钟产生模块和相位校正模块。 相位时钟生成块被配置为响应于一对输入时钟产生具有彼此不同的相位的多个相位时钟。 相位校正块被配置为生成最终输出内插相位时钟，其中每个相位时钟具有通过具有相邻相位的多个相位时钟调整的中心相位。