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    Sonet data transfer protocol between facility interfaces and cross-connect
    1.
    发明授权
    Sonet data transfer protocol between facility interfaces and cross-connect 失效
    Sonet数据传输协议在设备接口和交叉连接之间

    公开(公告)号：US5872780A

    公开(公告)日：1999-02-16

    申请号：US886724

    申请日：1992-05-21

    申请人： Sahabettin C. Demiray ,  Dale L. Krisher ,  William B. Weeber

    发明人： Sahabettin C. Demiray ,  Dale L. Krisher ,  William B. Weeber

    IPC分类号： H04J3/14 ,  H04J3/16 ,  H04Q11/04 ,  H04L12/52

    CPC分类号： H04J3/14 ,  H04J3/1611 ,  H04J2203/006 ,  Y10S370/907

    摘要： An internal signal within a SONET element has a transport format having overhead and payload mapped in a manner similar to the Synchronous Optical Network standard mapping, except having selected overhead bytes defined differently, including a byte used for communicating odd parity calculated over an odd number of bytes of a frame of the transport format to determine correct or incorrect parity, selected bytes used for inter-module automatic protection switching, and a pointer having a selected fixed value, along with an adjusted virtual tributary pointer in a virtual tributary mode.

    摘要翻译： SONET元件内的内部信号具有以类似于同步光网络标准映射的方式映射的开销和有效载荷的传输格式，除了具有不同定义的所选开销字节之外，包括用于传送在奇数个 传输格式的帧的字节以确定正确或不正确的奇偶校验，用于模块间自动保护切换的所选字节，以及具有选定的固定值的指针以及虚拟辅助模式中调整的虚拟辅助指针。

    Time division multiplexed synchronous state machine having state memory
    2.
    发明授权
    Time division multiplexed synchronous state machine having state memory 失效
    具有状态存储器的时分复用同步状态机

    公开(公告)号：US5809032A

    公开(公告)日：1998-09-15

    申请号：US783197

    申请日：1997-01-15

    申请人： William B. Weeber ,  Ertugrul Baydar ,  Sahabettin C. Demiray

    发明人： William B. Weeber ,  Ertugrul Baydar ,  Sahabettin C. Demiray

    IPC分类号： H04J3/06 ,  H04L7/04

    CPC分类号： H04J3/0623

    摘要： A receive SONET line interface includes an elastic store which receives and stores incoming signals from a pointer tracking circuit and retrieves stored signals for providing to a pointer generating circuit wherein, for both the pointer tracking and pointer generating circuits, separate state memories are provided for keeping track of the state of previous state pointer tracking and generating signals in time slots of repetitive frames of an incoming SONET signal.

    摘要翻译： 接收SONET线路接口包括弹性存储器，其接收并存储来自指针跟踪电路的输入信号，并检索存储的信号以提供给指针产生电路，其中，对于指针跟踪和指针产生电路两者，提供分离的状态存储器用于保持 跟踪前一状态指针跟踪的状态，并在输入的SONET信号的重复帧的时隙中产生信号。

    Sonet pointer interpretation system and method
    4.
    发明授权
    Sonet pointer interpretation system and method 失效
    SONET指针解释系统和方法

    公开(公告)号：US5210762A

    公开(公告)日：1993-05-11

    申请号：US771038

    申请日：1991-10-02

    申请人： William B. Weeber ,  Dale L. Krisher

    发明人： William B. Weeber ,  Dale L. Krisher

    IPC分类号： H04J3/06 ,  H04Q11/04

    CPC分类号： H04J3/0623 ,  H04J2203/006

    摘要： A SONET pointer interpretation in system which an Alarm Indication Signal (AIS) of a first type is interpreted as a subset of Loss of Pointer (LOP) of a first type. Specific events are defined for entering an AIS type 1 state and for exiting this state. Specific events are also defined for entering an LOP type 1 state and for exiting this state. Finally, a truth table is defined for mapping these states into a valid pointer (NORM) state, an AIS of a second type state and an LOP of a second type state.

    Calculation apparatus for performing algebraic and logic computations using iterative calculations and storage of intermediate results
    5.
    发明授权
    Calculation apparatus for performing algebraic and logic computations using iterative calculations and storage of intermediate results 失效

    公开(公告)号：US5528530A

    公开(公告)日：1996-06-18

    申请号：US371884

    申请日：1995-01-12

    申请人： William E. Powell ,  William B. Weeber ,  Manal E. Afify

    发明人： William E. Powell ,  William B. Weeber ,  Manal E. Afify

    IPC分类号： H04J3/07 ,  H04Q11/04 ,  G06F7/38

    CPC分类号： H04Q11/0414 ,  H04J3/076 ,  H04J2203/0003

    摘要： A desynchronizer (20) for desynchronizing data stored within synchronous payload envelopes of a synchronous communication protocol such as SONET (Synchronous Optical Network), provides for smoothing the periodically discontinuous clock signal associated with that data after the synchronous communication protocol overhead has been removed. The desynchronizer accommodates for shifts in the position of the payload envelope and hence, the data within the synchronous communication frame as well as adjustments within the data itself due to asynchronous bit stuff information. The desynchronizer utilizes a leak filter (26) having a linear branch (54) and an integrator branch (56), both branches having adjustable factors (61, 63, 65, 88, 90, 91, 93, 95, 100, 102, 105) regarding their operation, wherein the adjustable factors are selected depending upon threshold values (86, 87, 89, 62) which in turn are based upon the difference between the average write address and read address for the associated elastic store (22) within which the incoming data removed from the synchronous communication system frame is temporarily stored. The leak filter (26) forms part of a phase locked loop which in turn adjusts the read clock frequency (46) in a manner which minimizes overflow or underflow of the elastic store while simultaneously minimizing the rate of change of the read clock rate so as to limit jitter. A fault recovery apparatus forms part of the desynchronizer for enabling fastlock high gain factors (67, 97, 107) to quickly adjust the read clock when elastic store overflow or underflow occurs. The gain factors associated with both the linear branch and integrator branch are provisionable (118, 120) as well as elastic store size and thresholds resulting in a desynchronizer which can be modified to meet the particular jitter requirements of a particular synchronous communication system. A calculation engine (82) performs iterative calculations to generate the leak filter output value using a reduced number of logic gates for ASIC implementation.

    In-line piece-wise linear desynchronizer
    6.
    发明授权
    In-line piece-wise linear desynchronizer 失效
    在线PIECE-WISE线性去除器

    公开(公告)号：US5200982A

    公开(公告)日：1993-04-06

    申请号：US771037

    申请日：1991-10-02

    申请人： William B. Weeber

    发明人： William B. Weeber

    IPC分类号： H04J3/07

    CPC分类号： H04J3/076

    摘要： An in-line piece-wise linear desynchronizer eliminates the need for very low bandwidth analog, phase lock loops to smooth phase jumps caused by pointer changes such as those associated with a DS-1 signal mapped into a SONET VT 1.5 payload. The desynchronizer comprises a digital elastic store position detection circuit, a digital frame induced jitter filter, a digital leak rate filter, and a digital frequency synthesizer (VCO). The magnitude of the jitter can be reduced to any level by adjusting the digital VCO resolution and digital leak rate filter time constant. The desynchronizer produces a digitally synthesized output clock which can then be coupled to an analog/digital phase lock loop for smoothing high frequency jitter in the synthesized output clock, thereby providing an in-line interface function.

    Time division multiplexed synchronous state machine having state memory
    8.
    发明授权
    Time division multiplexed synchronous state machine having state memory 失效
    具有状态存储器的时分复用同步状态机

    公开(公告)号：US06449292B1

    公开(公告)日：2002-09-10

    申请号：US08924451

    申请日：1997-08-28

    申请人： William B. Weeber

    发明人： William B. Weeber

    IPC分类号： H04J306

    CPC分类号： H04J3/0623

    摘要： An implementation of a synchronous state machine, responsive to a time division multiplexed external input signal having plural time slots in a repetitive structure, has all of its flip-flop outputs hooked up to a state memory so that the state produced by each time slot is stored until that time slot is again repeated at the external input, at which point the stored state is recalled from memory for being input along with the incoming time slot data; in this way the hardware is shared between time slots. A substitution element is disclosed having a flip-flop with its output routed to memory and for providing a memory output as its output. A design methodology is taught whereby a state memory and a substitution element is substituted for each flip-flop in a synchronous state machine implemented for one time slot of a repeating pattern of time slots.

    摘要翻译： 同步状态机的实现，响应于具有重复结构中的多个时隙的时分复用外部输入信号，其所有触发器输出都挂接到状态存储器，使得每个时隙产生的状态为 存储直到在外部输入再次重复该时隙，此时从存储器调用存储状态以便与输入时隙数据一起输入; 以这种方式，硬件在时隙之间共享。 公开了一种替代元件，其具有触发器，其输出路由到存储器并用于提供存储器输出作为其输出。 教导了一种设计方法，其中状态存储器和替换元件代替实现在时隙的重复模式的一个时隙的同步状态机中的每个触发器。

    Phase detector for elastic store
    9.
    发明授权
    Phase detector for elastic store 失效
    弹性储物相检测仪

    公开(公告)号：US5461380A

    公开(公告)日：1995-10-24

    申请号：US183224

    申请日：1994-01-18

    申请人： Richard W. Peters ,  William B. Weeber

    发明人： Richard W. Peters ,  William B. Weeber

    IPC分类号： H04J3/07 ,  H03M9/00

    CPC分类号： H04J3/076

    摘要： A bit resolution phase detector can be realized for a parallel elastic store by comparing a write bit clock and a read bit clock to determine when stuff bits are required; upon detection of phase alignment between the write and read clocks, the phase detector will output a signal which will enable the insertion of a data bit into the stuff opportunity bit and cause the write clock to lag the read clock by one bit period.

    摘要翻译： 通过比较写位时钟和读位时钟来确定何时需要填充位，可以实现对于并行弹性存储器的位分辨率相位检测器; 在检测到写入和读取时钟之间的相位对准时，相位检测器将输出一个信号，该信号将使得能够将数据位插入到填充机会位中，并使写入时钟滞后于读取时钟一个位周期。

    Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same
    10.
    发明授权
    Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same 失效
    用于仿真串行伪随机发生器的并行伪随机发生器及其执行方法

    公开(公告)号：US5031129A

    公开(公告)日：1991-07-09

    申请号：US351175

    申请日：1989-05-12

    申请人： William E. Powell ,  William B. Weeber ,  Georges A. C. Roger

    发明人： William E. Powell ,  William B. Weeber ,  Georges A. C. Roger

    IPC分类号： G06F7/58 ,  H03K3/84 ,  H04J3/00 ,  H04L9/22 ,  H04L25/03

    CPC分类号： H04L25/03872

    摘要： A parallel pseudo-random generator emulates a serial pseudo-random generator which in turn is defined by a polynomial of the type 1+x.sup.M + . . . +x.sup.P ; that is, wherein the serial outputs are generated such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values. The parallel pseudo-random generator comprises latches and Exclusive OR gates, the number of latches and Exclusive OR gates each being at least equal to the polynomial order of the serial pseudo-random generator defining polynomial. The outputs of the latches represent the outputs of the parallel pseudo-random generator and may be used to scramble data on parallel data lines. A method is disclosed for determining the interconnects between the latch outputs and the Exclusive OR gate inputs based upon the number of latches and the serial pseudo-random generator defining polynomial.