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8 条记录 (耗时 0.013 秒)

    De-Glitch Circuit
    1.
    发明申请
    De-Glitch Circuit 有权
    去毛刺电路

    公开(公告)号：US20080164909A1

    公开(公告)日：2008-07-10

    申请号：US11686828

    申请日：2007-03-15

    申请人： Darmin Jin ,  Brian Cheung

    发明人： Darmin Jin ,  Brian Cheung

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： H03K5/1252

    摘要： A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a “de-glitching” time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.

    摘要翻译： 一种用于对输入信号进行去毛刺的数字逻辑电路和方法。 电路消除了在输入信号从0到1或从1到0之间的每个转换之后的“去毛刺”时间段期间发生的失真。该电路可以从输入信号中去除这种失真而基本上不延迟输入信号。 具体地说，插入的延迟可以远小于除毛时间段的持续时间。 一个实施例包括第一和第二设置复位触发器，每个触发器具有连接的输入端以接收输入信号并且具有连接到多数电路的输出。 延迟电路还接收输入信号并向多数电路提供输出。 其他实施例用包括逻辑门的电路代替多数电路。

    APPARATUS AND METHOD FOR HIGH VOLTAGE SWITCHES
    3.
    发明申请
    APPARATUS AND METHOD FOR HIGH VOLTAGE SWITCHES 有权
    高压开关的装置和方法

    公开(公告)号：US20130300485A1

    公开(公告)日：2013-11-14

    申请号：US13468957

    申请日：2012-05-10

    申请人： Darmin Jin ,  William Chau ,  Brian Cheung

    发明人： Darmin Jin ,  William Chau ,  Brian Cheung

    IPC分类号： H03L5/00 ,  H03K17/56

    CPC分类号： G01R31/31924 ,  H03K17/56 ,  H03K19/017509 ,  H03K2217/0081

    摘要： Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

    摘要翻译： 公开了一种用于通过高压开关耦合半导体器件的高电压的装置和方法。 高压开关包括开关和电平转换器。 开关定义在电压源和电压输出之间。 使能线耦合到开关的第一晶体管。 电平移位器包括输入和输出。 表征线耦合到电平移位器的输入，并且电平移位器的输出耦合到开关的第二晶体管。 电平移位器还包括电源轨，该电源轨耦合到第一晶体管和第二晶体管之间的开关。

    Apparatus and method for high voltage switches
    6.
    发明授权
    Apparatus and method for high voltage switches 有权
    高压开关的装置和方法

    公开(公告)号：US08884679B2

    公开(公告)日：2014-11-11

    申请号：US13468957

    申请日：2012-05-10

    申请人： Darmin Jin ,  William Chau ,  Brian Cheung

    发明人： Darmin Jin ,  William Chau ,  Brian Cheung

    IPC分类号： H03L5/00

    CPC分类号： G01R31/31924 ,  H03K17/56 ,  H03K19/017509 ,  H03K2217/0081

    摘要： Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

    摘要翻译： 公开了一种用于通过高压开关耦合半导体器件的高电压的装置和方法。 高压开关包括开关和电平转换器。 开关定义在电压源和电压输出之间。 使能线耦合到开关的第一晶体管。 电平移位器包括输入和输出。 表征线耦合到电平移位器的输入，并且电平移位器的输出耦合到开关的第二晶体管。 电平移位器还包括电源轨，该电源轨耦合到第一晶体管和第二晶体管之间的开关。

    De-glitch circuit
    7.
    发明授权
    De-glitch circuit 有权
    去毛刺电路

    公开(公告)号：US07557643B2

    公开(公告)日：2009-07-07

    申请号：US11686828

    申请日：2007-03-15

    申请人： Darmin Jin ,  Brian Cheung

    发明人： Darmin Jin ,  Brian Cheung

    IPC分类号： H03K5/00

    CPC分类号： H03K5/1252

    摘要： A digital logic circuit and method for de-glitching an input signal. The circuit removes distortion that occurs during a “de-glitching” time period that follows each transition of the input signal from 0 to 1 or from 1 to 0. The circuit can remove such distortion from the input signal without substantially delaying the input signal. Specifically, the delay interposed can be much less than the duration of the de-glitching time period. One embodiment includes first and second Set-Reset flip-flops each having an input connected to receive the input signal and having an output connected to a majority circuit. A delay circuit also receives the input signal and provides an output to the majority circuit. Other embodiments replace the majority circuit with a circuit including logic gates.

    摘要翻译： 一种用于对输入信号进行去毛刺的数字逻辑电路和方法。 电路消除了在输入信号从0到1或从1到0之间的每个转换之后的“去毛刺”时间段期间发生的失真。该电路可以从输入信号中去除这种失真而基本上不延迟输入信号。 具体地说，插入的延迟可以远小于除毛时间段的持续时间。 一个实施例包括第一和第二设置复位触发器，每个触发器具有连接的输入端以接收输入信号并且具有连接到多数电路的输出。 延迟电路还接收输入信号并向多数电路提供输出。 其他实施例用包括逻辑门的电路代替多数电路。