公开(公告)号：US06797633B2

公开(公告)日：2004-09-28

申请号：US09966605

申请日：2001-09-28

Applicant: Ping Jiang ,  Robert Kraft ,  Kenneth J. Newton ,  Daty M. Rogers

Inventor： Ping Jiang ,  Robert Kraft ,  Kenneth J. Newton ,  Daty M. Rogers

IPC: H01L21302

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76826

Abstract: After via etch, a low-k dielectric layer (104) is treated with an in-situ O2 plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.

Abstract translation: 在经过蚀刻之后，用原位O 2等离子体处理低k电介质层（104）。 抵抗中毒是由导致低k膜（104）如OSG和DUV抗蚀剂（130,132）之间的相互作用的N源引起的。 原位等离子体处理立即消除中毒源，以减少或消除沟槽图案化的中毒。

公开(公告)号：US06930028B1

公开(公告)日：2005-08-16

申请号：US09092115

申请日：1998-06-05

Applicant: Maureen A. Hanratty ,  Daty M. Rogers ,  Qizhi He ,  Wei William Lee

Inventor： Maureen A. Hanratty ,  Daty M. Rogers ,  Qizhi He ,  Wei William Lee

IPC: H01L21/027 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/76834 ,  H01L21/76838 ,  H01L29/665 ,  Y10S438/952

Abstract: The present invention provides integrated circuit fabrication with a silicon oxynitride antireflective layer for gate location plus patterned photoresist linewidth reduction for gate length definition followed by interconnect definition without patterned photoresist linewidth reduction. This has the advantages of an antireflective layer compatible with linewidth reduction and polysilicon etching.

Abstract translation: 本发明提供集成电路制造，其具有用于栅极位置的硅氧氮化物抗反射层，以及用于栅极长度定义的图案化的光致抗蚀剂线宽降低，随后是互连定义，而没有图案化的光致抗蚀剂线宽降低。 这具有与线宽减小和多晶硅蚀刻相兼容的抗反射层的优点。