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    Semiconductor wafer polisher and method
    2.
    发明授权
    Semiconductor wafer polisher and method 失效
    半导体晶片抛光机及方法

    公开(公告)号：US5422316A

    公开(公告)日：1995-06-06

    申请号：US214969

    申请日：1994-03-18

    申请人： Ankur H. Desai ,  Michael S. Wisnieski ,  David I. Golland

    发明人： Ankur H. Desai ,  Michael S. Wisnieski ,  David I. Golland

    IPC分类号： B24B37/013 ,  B24B37/08 ,  B24B37/28 ,  H01L21/465

    CPC分类号： B24B37/08 ,  B24B37/013 ,  B24B37/28 ,  Y10S438/977

    摘要： A semiconductor wafer polisher of the present invention for polishing at least one semiconductor wafer to flatten a first face of the wafer and reduce the thickness of the wafer from an initial thickness t.sub.1 to a predetermined final thickness t.sub.2. The polisher comprises a first surface including a polishing surface portion, a second surface including a second surface portion, and a wafer carrier for holding the semiconductor wafer between the polishing surface portion and the second surface portion. At least one polishing limiter is between the first and second surfaces for limiting the reduction in thickness of the wafer. The wafer carrier and polishing limiter are integrally formed such that the polishing limiter and wafer carrier constitute a single unitary piece. The polishing limiter has at least one rubbing surface adapted for rubbing against one of the first and second surfaces and is sized and configured such that the rubbing surface is spaced axially from the one of the first and second surfaces when the semiconductor wafer has the thickness t.sub.1 and such that the rubbing surface rubs against the one of the first and second surfaces and the polishing limiter extends from the second surface to the first surface when the semiconductor wafer has the thickness t.sub.2. The polishing limiter has a greater resistance to polishing than that of the semiconductor wafer such that the polishing limiter prevents the polishing surface and the second surface portion from further moving axially toward each other when the polishing limiter extends from the second surface to the first surface to prevent the wafer from being reduced in thickness beyond the thickness t.sub.2.

    摘要翻译： 本发明的半导体晶片抛光机用于抛光至少一个半导体晶片以使晶片的第一面平坦化并将晶片的厚度从初始厚度t1减小到预定的最终厚度t2。 抛光机包括包括抛光表面部分的第一表面，包括第二表面部分的第二表面和用于将半导体晶片保持在抛光表面部分和第二表面部分之间的晶片载体。 在第一和第二表面之间至少有一个抛光限制器用于限制晶片厚度的减小。 晶片载体和抛光限制器一体形成，使得抛光限制器和晶片载体构成单个整体。 抛光限制器具有适于摩擦第一和第二表面中的一个的至少一个摩擦表面，并且其尺寸和构造使得当半导体晶片具有厚度t1时，摩擦表面与第一和第二表面中的一个轴向间隔开 并且使得当半导体晶片具有厚度t2时，摩擦表面摩擦第一表面和第二表面之一，并且抛光限制器从第二表面延伸到第一表面。 抛光限制器具有比半导体晶片更大的抛光阻力，使得当抛光限制器从第二表面延伸到第一表面时，抛光限制器防止抛光表面和第二表面部分进一步朝向彼此轴向移动， 防止晶片厚度减小超过厚度t2。

    Edge stripped BESOI wafer
    4.
    发明授权
    Edge stripped BESOI wafer 失效
    边缘剥离BESOI晶圆

    公开(公告)号：US5834812A

    公开(公告)日：1998-11-10

    申请号：US820593

    申请日：1997-03-19

    申请人： David I. Golland ,  Robert A. Craven ,  Ronald D. Bartram

    发明人： David I. Golland ,  Robert A. Craven ,  Ronald D. Bartram

    IPC分类号： H01L21/304 ,  H01L21/02 ,  H01L21/762 ,  H01L27/12 ,  H01L21/20

    CPC分类号： H01L21/76251 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S148/161 ,  Y10S438/977

    摘要： A process for stripping the outer edge of a bonded BESOI wafer. The bonded BESOI wafer comprises a handle wafer, an oxide layer on one surface of the handle wafer, a device layer bonded to the oxide layer, and a p.sup.+ etch-stop layer on the device layer having an exposed face. The process comprises masking the exposed face of the p.sup.+ etch-stop layer, and abrading the periphery of the BESOI wafer to remove edge margins of the p.sup.+ etch-stop layer and device layer.

    摘要翻译： 剥离粘结的BESOI晶片的外边缘的方法。 结合的BESOI晶片包括处理晶片，在处理晶片的一个表面上的氧化物层，结合到氧化物层的器件层，以及在具有暴露面的器件层上的p +蚀刻停止层。 该方法包括掩蔽p +蚀刻停止层的暴露面，以及研磨BESOI晶片的周边以去除p +蚀刻停止层和器件层的边缘。