公开(公告)号：US08214699B2

公开(公告)日：2012-07-03

申请号：US12147670

申请日：2008-06-27

申请人： Igor Arsovski ,  David J. Wager ,  Michael A. Ziegerhofer

发明人： Igor Arsovski ,  David J. Wager ,  Michael A. Ziegerhofer

IPC分类号： G11C29/12

CPC分类号： G06F13/4243

摘要： Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal. Thus, in the performance screening mode, the digital integrated circuit is effectively converted into a performance screen ring oscillator (PSRO), the output of which can be monitored to determine whether performance criteria for the digital integrated circuit are met.

摘要翻译： 公开了具有数字集成电路的半导体芯片，例如存储器件（例如，静态随机存取存储器（SRAM）阵列，动态随机存取存储器（DRAM）阵列，内容可寻址存储器（CAM）阵列等）），其可以 选择性地在功能模式或性能筛选模式下操作。 在功能模式中，使用由外部信号发生器提供的第一信号来激活电路中的第一设备，并且作为响应，电路中的第二设备输出数据输出信号。 在演奏屏蔽模式中，第二信号由内部信号发生器基于数据输出信号内部产生。 然后该第二信号用于激活电路中的第一设备，并且作为响应，第二设备输出数据输出信号。 因此，在性能筛选模式下，数字集成电路被有效地转换为性能屏幕环形振荡器（PSRO），其输出可以被监视以确定是否满足数字集成电路的性能标准。

公开(公告)号：US08099688B2

公开(公告)日：2012-01-17

申请号：US11985961

申请日：2007-11-19

申请人： Wayne F. Ellis ,  Randy W. Mann ,  David J. Wager ,  Robert C. Wong

发明人： Wayne F. Ellis ,  Randy W. Mann ,  David J. Wager ,  Robert C. Wong

IPC分类号： G06F17/50

CPC分类号： G11C11/413 ,  G11C5/14

摘要： A design process includes inputting a design file representing a circuit design embodied in a non-transitory computer-readable medium, and using a computer to translate the circuit design into a netlist. The netlist comprises a representation of a plurality of wires, transistors, and logic gates, and is stored in the non-transitory computer-readable medium. When executed by the computer, the netlist produces the circuit design. The circuit design comprises a static random access memory (“SRAM”) including a plurality of SRAM cells arranged in an array, including a plurality of rows and a plurality of columns, and a plurality of column voltage control circuits corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply and is operable to temporarily reduce a voltage upon arrival of a bit select signal provided to power supply inputs of a plurality of SRAM cells belonging to a selected column of the plurality of columns. The selected column is selected during a write operation in which a bit is written to one of the plurality of SRAM cells belonging to the selected column. Each column voltage control circuit includes an NFET and a pair of PFETs. Each NFET and pair of PFETs has a conduction path directly connected between the output of the power supply and the power supply inputs of the plurality of SRAM cells.

摘要翻译： 设计过程包括输入表示在非暂时计算机可读介质中体现的电路设计的设计文件，并使用计算机将电路设计转换成网表。 网表包括多个线，晶体管和逻辑门的表示，并且存储在非暂时计算机可读介质中。 当由计算机执行时，网表产生电路设计。 该电路设计包括一个静态随机存取存储器（“SRAM”），它包括多个排列成阵列的SRAM单元，包括多行和多列，以及多个列电压控制电路， 阵列的多列。 多个电压控制电路中的每一个耦合到电源的输出，并且可操作以在到达时临时减小提供给属于所选择的列的所选列的多个SRAM单元的电源输入的位选择信号 多列。 在写入操作期间选择所选列，其中将位写入属于所选列的多个SRAM单元之一。 每列电压控制电路包括NFET和一对PFET。 每个NFET和一对PFET具有直接连接在电源的输出端与多个SRAM单元的电源输入端之间的导通路径。

公开(公告)号：US20090327620A1

公开(公告)日：2009-12-31

申请号：US12147670

申请日：2008-06-27

申请人： Igor Arsovski ,  David J. Wager ,  Michael A. Ziegerhofer

发明人： Igor Arsovski ,  David J. Wager ,  Michael A. Ziegerhofer

IPC分类号： G06F13/00

CPC分类号： G06F13/4243

摘要： Disclosed is a semiconductor chip with a digital integrated circuit, such as a memory device (e.g., static random access memory (SRAM) arrays, dynamic random access memory (DRAM) arrays, content addressable memory (CAM) arrays, etc), that can be selectively operated in either a functional mode or in a performance screening mode. In the functional mode, a first signal supplied by an external signal generator is used to activate a first device in the circuit and, in response, a second device in the circuit outputs a data output signal. In the performance screening mode, a second signal is internally generated by an internal signal generator based on the data output signal. This second signal is then used to activate the first device in the circuit and, in response, the second device outputs the data output signal. Thus, in the performance screening mode, the digital integrated circuit is effectively converted into a performance screen ring oscillator (PSRO), the output of which can be monitored to determine whether performance criteria for the digital integrated circuit are met.

摘要翻译： 公开了具有数字集成电路的半导体芯片，例如存储器件（例如，静态随机存取存储器（SRAM）阵列，动态随机存取存储器（DRAM）阵列，内容可寻址存储器（CAM）阵列等）），其可以 选择性地在功能模式或性能筛选模式下操作。 在功能模式中，使用由外部信号发生器提供的第一信号来激活电路中的第一设备，并且作为响应，电路中的第二设备输出数据输出信号。 在演奏屏蔽模式中，第二信号由内部信号发生器基于数据输出信号内部产生。 然后该第二信号用于激活电路中的第一设备，并且作为响应，第二设备输出数据输出信号。 因此，在性能筛选模式下，数字集成电路被有效地转换为性能屏幕环形振荡器（PSRO），其输出可以被监视以确定是否满足数字集成电路的性能标准。

公开(公告)号：US20090129191A1

公开(公告)日：2009-05-21

申请号：US11985961

申请日：2007-11-19

申请人： Wayne F. Ellis ,  Randy W. Mann ,  David J. Wager ,  Robert C. Wong

发明人： Wayne F. Ellis ,  Randy W. Mann ,  David J. Wager ,  Robert C. Wong

IPC分类号： G11C5/14

CPC分类号： G11C11/413 ,  G11C5/14

摘要： A design structure including a static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes voltage control circuits corresponding to respective ones of the plurality of columns of the array, each coupled to an output of a power supply. Each voltage control circuit temporarily reduces a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The power supply voltage to the selected column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

摘要翻译： 提供了包括静态随机存取存储器（“SRAM”）的设计结构，其包括以阵列布置的多个SRAM单元。 阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的电压控制电路，每个耦合到电源的输出端。 每个电压控制电路暂时降低提供给属于SRAM的选定列列的多个SRAM单元的电源输入的电压。 在将位写入属于所选列的SRAM单元之一的写操作期间，对所选列的电源电压降低。

公开(公告)号：US06333872B1

公开(公告)日：2001-12-25

申请号：US09707201

申请日：2000-11-06

申请人： Michael R. Ouellette ,  David J. Wager

发明人： Michael R. Ouellette ,  David J. Wager

IPC分类号： G11C700

CPC分类号： G11C29/14

摘要： A structure and method for testing multi-port SRAM cells includes a test controller connected to at least one multi-port SRAM cell (the test controller is adapted to store a pattern into the multi-port SRAM cell and generate a stability test restore clamp), a read/write controller connected to the multi-port SRAM cell (the read/write controller is adapted to simultaneously activate a plurality of wordline ports on the multi-port SRAM cell while the stability test restore clamp is enabled), and a timing control circuit connected to the read/write controller. The timing control circuit is adapted to vary an activation time of the wordline ports. The read/write controller reads from the multi-port SRAM after the stability test restore clamp is deactivated. The read/write controller activates the wordline ports for each multi-port SRAM cell in an array sequentially while all bitlines in the array are held on by the stability test restore clamp. The structure also includes a logic device connected to the test controller adapted to prevent the stability test restore clamp from being enabled unless a test is being performed. The timing control circuit is adapted to be selectively externally controllable to vary the activation time of the wordline ports. The timing control circuit can include a plurality of delay units adapted to be selectively engaged to vary the activation time of the wordline ports. The stability test restore clamp is enabled for at least a wordline pulse.

摘要翻译： 用于测试多端口SRAM单元的结构和方法包括连接到至少一个多端口SRAM单元的测试控制器（测试控制器适于将模式存储到多端口SRAM单元中并产生稳定性测试恢复钳位） ，连接到多端口SRAM单元的读/写控制器（读/写控制器适于同时激活多端口SRAM单元上的多个字线端口，同时稳定性测试恢复钳位被使能），以及定时 控制电路连接到读/写控制器。 定时控制电路适于改变字线端口的激活时间。 在禁用稳定性测试恢复钳位之后，读/写控制器从多端口SRAM读取。 读/写控制器顺序激活阵列中每个多端口SRAM单元的字线端口，同时阵列中的所有位线均由稳定性测试恢复钳位保持。 该结构还包括连接到测试控制器的逻辑设备，其适于防止稳定性测试恢复钳位被启用，除非正在执行测试。 定时控制电路适于选择性地可外部控制以改变字线端口的激活时间。 定时控制电路可以包括适于选择性地接合以改变字线端口的激活时间的多个延迟单元。 稳定性测试恢复钳位使能至少一个字线脉冲。

公开(公告)号：US07466604B2

公开(公告)日：2008-12-16

申请号：US11998948

申请日：2007-12-03

申请人： Wayne F. Ellis ,  Randy W. Mann ,  David J. Wager ,  Robert C. Wong

发明人： Wayne F. Ellis ,  Randy W. Mann ,  David J. Wager ,  Robert C. Wong

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C5/14 ,  G11C11/413

摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array having a plurality of portions. The SRAM includes a plurality of voltage control circuits corresponding to respective ones of the plurality of portions of the array. Each of the plurality of voltage control circuits is coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected one of the plurality of portions of the SRAM. The power supply voltage to the selected portion is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected portion.

摘要翻译： 提供了一种静态随机存取存储器（“SRAM”），其包括以具有多个部分的阵列布置的多个SRAM单元。 SRAM包括对应于阵列的多个部分中的相应部分的多个电压控制电路。 多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于多个所选择的多个SRAM单元中的多个SRAM单元的电源输入的电压的功能 的SRAM部分。 在将位写入属于所选部分的SRAM单元之一的写操作期间，所选部分的电源电压降低。

公开(公告)号：US07313032B2

公开(公告)日：2007-12-25

申请号：US11164556

申请日：2005-11-29

申请人： Wayne F. Ellis ,  Randy W. Mann ,  David J. Wager ,  Robert C. Wong

发明人： Wayne F. Ellis ,  Randy W. Mann ,  David J. Wager ,  Robert C. Wong

IPC分类号： G11C5/14 ,  G11C11/00

CPC分类号： G11C5/14 ,  G11C11/413

摘要： A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones of the plurality of columns of the array. Each of the plurality of voltage control circuits are coupled to an output of a power supply, each voltage control circuit having a function to temporarily reduce a voltage provided to power supply inputs of a plurality of SRAM cells that belong to a selected column of columns of the SRAM. The selected column is selected and the power supply voltage to that column is reduced during a write operation in which a bit is written to one of the SRAM cells belonging to the selected column.

摘要翻译： 提供了包括以阵列布置的多个SRAM单元的静态随机存取存储器（“SRAM”）。 阵列包括多个行和多个列。 SRAM包括对应于阵列的多个列中的相应列的多个电压控制。 多个电压控制电路中的每一个耦合到电源的输出，每个电压控制电路具有临时降低提供给属于所选列列的多个SRAM单元的电源输入的电压的功能 SRAM。 选择的列被选择，并且在将位写入属于所选列的SRAM单元之一的写操作期间，该列的电源电压减小。

公开(公告)号：US07210085B2

公开(公告)日：2007-04-24

申请号：US10725668

申请日：2003-12-02

申请人： Ciaran J. Brennan ,  Steven M. Eustis ,  Michael T. Fragano ,  Michael R. Ouellette ,  Neelesh G. Pai ,  Jeremy P. Rowland ,  Kevin M. Tompsett ,  David J. Wager

发明人： Ciaran J. Brennan ,  Steven M. Eustis ,  Michael T. Fragano ,  Michael R. Ouellette ,  Neelesh G. Pai ,  Jeremy P. Rowland ,  Kevin M. Tompsett ,  David J. Wager

IPC分类号： G01R31/28

CPC分类号： G11C29/4401 ,  G11C11/41 ,  G11C29/44 ,  G11C29/70 ,  G11C2029/0401

摘要： A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.

摘要翻译： 一种制造具有包括多个存储单元的嵌入式存储器的装置的方法。 在制造测试期间，通过内置的自我测试将第一测试应力施加到多个存储单元的选定单元。 识别至少一个弱记忆体单元。 至少一个弱记忆体被修复。 第二个测试应力应用于所选择的细胞和修复的细胞与内置的自我测试。