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1.发明授权Method and apparatus for test and repair of marginally functional SRAM cells 失效用于边缘功能SRAM单元的测试和修复的方法和装置公开(公告)号：US07210085B2
公开(公告)日：2007-04-24
申请号：US10725668
申请日：2003-12-02
申请人： Ciaran J. Brennan , Steven M. Eustis , Michael T. Fragano , Michael R. Ouellette , Neelesh G. Pai , Jeremy P. Rowland , Kevin M. Tompsett , David J. Wager
发明人： Ciaran J. Brennan , Steven M. Eustis , Michael T. Fragano , Michael R. Ouellette , Neelesh G. Pai , Jeremy P. Rowland , Kevin M. Tompsett , David J. Wager
IPC分类号： G01R31/28
CPC分类号： G11C29/4401 , G11C11/41 , G11C29/44 , G11C29/70 , G11C2029/0401
摘要： A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.
摘要翻译： 一种制造具有包括多个存储单元的嵌入式存储器的装置的方法。 在制造测试期间，通过内置的自我测试将第一测试应力施加到多个存储单元的选定单元。 识别至少一个弱记忆体单元。 至少一个弱记忆体被修复。 第二个测试应力应用于所选择的细胞和修复的细胞与内置的自我测试。
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公开(公告)号：US06944075B1
公开(公告)日：2005-09-13
申请号：US10905451
申请日：2005-01-05
IPC分类号： G11C7/00
CPC分类号： G11C29/808 , G11C11/41 , G11C29/816
摘要： A method of assigning bits to redundant regions for variable bit redundancy region boundaries in a compliable memory such as a 1-port SRAM is provided. Methods include allocating bits between the redundant regions in nearly equal proportions while minimizing the amount of chip real estate consumed by the memory. Methods also includes allocating bits in equal portions between redundant regions while occupying slightly more memory chip real estate. Methods also allocate bits into redundant regions with a simplified procedure which may or may not allocate bits into the redundant regions in equal proportions. All of the methods allow the total number of memory bits in the complied memory to be re-defined while maintaining the same allocation characteristics for each method. Accordingly, the methods allow efficient use of redundant memory bits while also conserving chip real estate or offering simplified allocation steps.
摘要翻译： 提供了一种将比特分配给诸如1端口SRAM的可复制存储器中的可变位冗余区域边界的冗余区域的方法。 方法包括以几乎相等的比例在冗余区域之间分配比特，同时最小化存储器消耗的芯片空间的量。 方法还包括在冗余区域之间相等分配比特，同时占据稍微更多的存储器芯片空间。 方法还使用简化的过程将比特分配到冗余区域中，这可以或可以不以相等比例将比特分配到冗余区域中。 所有这些方法允许重新定义编译存储器中的存储器位的总数，同时为每种方法保持相同的分配特性。 因此，这些方法允许有效地使用冗余存储器位，同时还节省芯片空间或提供简化的分配步骤。
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公开(公告)号：US06928377B2
公开(公告)日：2005-08-09
申请号：US10658940
申请日：2003-09-09
CPC分类号： G11C29/846 , G11C29/44 , G11C29/4401 , G11C29/72 , G11C2029/1208
摘要： Self-test architectures are provided to implement data column and row redundancy with a totally integrated self-test and repair capability in a Random Access Memory (RAM), either a Dynamic RAM (DRAM) or a Static Ram (SRAM), and are particularly applicable to compileable memories and to embedded RAM within microprocessor or logic chips. The invention uses two passes of self-test of a memory. The first pass of self-test determines the worst failing column, the column with the largest number of unique failing row addresses. After completion of the first pass of self-test, the spare column is allocated to replace the worst failing column. In the second pass of self-test, the BIST (Built In Self-Test) collects unique failing row addresses as it does today for memories with spare rows only. At the completion of the second pass of self-test, the spare rows are then allocated. Once the second pass of self-test is completed, the column and unique failing row addresses are transported to the e-fuse macros and permanently stored in the chip.
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4.发明授权Bypass structure for a memory device and method to reduce unknown test values 有权用于存储器件的旁路结构和减少未知测试值的方法公开(公告)号：US08917566B2
公开(公告)日：2014-12-23
申请号：US13444229
申请日：2012-04-11
申请人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
发明人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
IPC分类号： G11C7/00
CPC分类号： G11C29/56004
摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.
摘要翻译： 本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。 在一个实施例中，公开了一种用于存储器件的旁路结构。 旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于 断言测试信号，使得来自存储器设备的输出的未知数据被旁路。
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5.发明申请BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN TEST VALUES 有权用于存储器件的旁路结构和减少未知测试值的方法公开(公告)号：US20130272072A1
公开(公告)日：2013-10-17
申请号：US13444229
申请日：2012-04-11
申请人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
发明人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
IPC分类号： G11C7/10
CPC分类号： G11C29/56004
摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.
摘要翻译： 本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。 在一个实施例中，公开了一种用于存储器件的旁路结构。 旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于 断言测试信号，使得来自存储器设备的输出的未知数据被旁路。
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公开(公告)号：US07251757B2
公开(公告)日：2007-07-31
申请号：US10727239
申请日：2003-12-02
CPC分类号： G11C29/1201 , G11C29/44 , G11C2029/0405 , G11C2029/3202 , G11C2029/3602
摘要： A structure comprising a memory chip and a tester for testing the memory chip, and a method for operating the structure. The memory chip comprises a BIST (Built-in Self Test) circuit, a plurality of RAMs (Random Access Memories). A first RAM is selected for testing by scanning in a select value into a RAM select register in the BIST. While the BIST performs a first testing pass for the first RAM, the tester collects cycle numbers of the failing cycles. Then, the BIST performs a second testing pass for the first RAM. At each failing cycle identified during the first testing pass, the BIST pauses so that the content of the location of the first RAM associated with the failing cycle and the state of the BIST can be extracted out of the memory chip. The testing procedures for the other RAMs are similar to that of the first RAM.
摘要翻译： 一种包括存储器芯片和用于测试存储芯片的测试器的结构，以及用于操作该结构的方法。 存储器芯片包括BIST（内置自检）电路，多个RAM（随机存取存储器）。 通过将选择值扫描到BIST中的RAM选择寄存器中，选择第一个RAM进行测试。 当BIST执行第一个RAM的第一次测试通过时，测试仪将收集故障周期的周期数。 然后，BIST对第一个RAM执行第二次测试。 在第一测试通过期间识别的每个故障循环中，BIST暂停，使得与故障循环相关联的第一RAM的位置的内容和BIST的状态的内容可以从存储器芯片中提取出来。 其他RAM的测试程序与第一个RAM的测试程序相似。
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公开(公告)号：US06430072B1
公开(公告)日：2002-08-06
申请号：US09682638
申请日：2001-10-01
IPC分类号： G11C1500
摘要： A method and structure for content addressable memory structure having a memory array of words, each word having multiple memory bits and a plurality of matchlines. Each of the matchlines is connected to one of the words and a matchline compare circuit is connected to the matchlines and is adapted to test all of the words individually. The matchline compare circuit includes a plurality of comparators equal in number to a number of the words, such that each word is connected to a dedicated comparator to allow each word in the memory array to be individually tested.
摘要翻译： 一种用于内容可寻址存储器结构的方法和结构，其具有字的存储器阵列，每个字具有多个存储器位和多个匹配线。 每个匹配线连接到一个字，并且匹配线比较电路连接到匹配线，并且适于单独测试所有单词。 匹配线比较电路包括多个比较器，其数量与字数相等，使得每个字连接到专用比较器以允许单独测试存储器阵列中的每个字。
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8.发明申请COMPILABLE MEMORY STRUCTURE AND TEST METHODOLOGY FOR BOTH ASIC AND FOUNDRY TEST ENVIRONMENTS 审中-公开可编程存储器结构和测试方法用于两个ASIC和基准测试环境公开(公告)号：US20080256405A1
公开(公告)日：2008-10-16
申请号：US12143007
申请日：2008-06-20
IPC分类号： G01R31/3185 , G06F11/25 , G01R31/3187
CPC分类号： G11C29/48 , G11C29/1201 , G11C2029/3202
摘要： A method of implementing a compilable memory structure configured for supporting multiple test methodologies includes configuring a first plurality of multiplexers for selectively coupling at least one data input path and at least one address path between an external customer connection and a corresponding internal memory connection associated therewith. A second multiplexer is configured for selectively coupling an input of a test latch between a functional memory array connection and a memory logic connection, the memory logic connection coupled to the at least one data input path, with an output of the test latch defining a data out customer connection. Flush logic is configured to direct data from the memory logic connection to the data out customer connection during a test of logic associated with a customer chip, facilitating observation of the memory logic connection at the customer chip.
摘要翻译： 实现被配置为支持多个测试方法的可编译存储器结构的方法包括配置第一多个多路复用器，用于选择性地耦合至少一个数据输入路径和外部客户连接与与其相关联的对应内部存储器连接之间的至少一个地址路径。 第二多路复用器被配置为选择性地耦合功能存储器阵列连接和存储器逻辑连接之间的测试锁存器的输入，存储器逻辑连接耦合到至少一个数据输入路径，测试锁存器的输出定义数据 客户连接。 冲洗逻辑被配置为在与客户芯片相关联的逻辑的测试期间将数据从存储器逻辑连接引导到数据输出客户连接，以便于观察客户芯片上的存储器逻辑连接。
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公开(公告)号：US07937632B2
公开(公告)日：2011-05-03
申请号：US12144703
申请日：2008-06-24
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/48 , G11C2029/0401
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括耦合到数据处理单元输入的输入寄存器和测试操作模式和功能操作模式。 在测试模式操作中，寄存器以时钟模式操作，使得在测试操作模式期间，寄存器响应于时钟信号将数据传播到数据处理单元。 在功能操作模式中，寄存器以数据刷新模式运行，使得寄存器响应于数据将数据传播到数据处理单元。 功能模式由刷新使能信号使能，测试模式通过刷新使能信号的相反状态使能。
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公开(公告)号：US20090319818A1
公开(公告)日：2009-12-24
申请号：US12144686
申请日：2008-06-24
IPC分类号： G06F1/06
CPC分类号： G01R31/318552 , G11C7/02 , G11C7/04 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C29/1201 , G11C29/12015 , G11C29/48 , G11C2029/5602 , G11C2207/104
摘要： A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.
摘要翻译： 提供一种用于操作第一单元和提供其数据的第二单元之间的接口的方法。 该方法包括在LSSD_B和LSSD_C时钟之间的切换控制和系统时钟（CLK），以提供测试操作模式和功能操作模式，以根据单元运行的条件来优化建立和保持时间。 在测试模式下，数据由LSSD_C时钟启动。 在功能模式下，数据由系统时钟（CLK）发送到RAM。 还提供了一种方法来确定哪些存储器输入应该使用提供足够的建立和保持余量的电路。
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