公开(公告)号：US08842482B1

公开(公告)日：2014-09-23

申请号：US13538291

申请日：2012-06-29

申请人： David Kunst ,  Hans Van Antwerpen

发明人： David Kunst ,  Hans Van Antwerpen

IPC分类号： G11C7/06 ,  G11C11/34 ,  G11C16/04

CPC分类号： G11C7/20 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C7/227 ,  G11C17/16 ,  G11C2029/4402

摘要： Embodiments of a circuit and method for setting initial trim bits in an integrated circuit (IC) are described. The circuit includes a memory array including a plurality of trim bit cells to store and provide trim bits to trim registers in a main circuit of the IC following energizing of the IC. The memory array further includes replica bit circuitry to generate a number of replica bits. A logic circuit coupled to the memory array and the main circuit of the IC is configured to receive the replica bits, and to provide a signal to the IC that indicates when the trim bits are valid. In one embodiment, the circuit further includes redundancy check logic configured to receive a number of the trim bits from the memory array, compare the number of trim bits to a pre-determined or computed value, and to provide a BITS_OK signal to the logic circuit.

摘要翻译： 描述用于设置集成电路（IC）中的初始修整位的电路和方法的实施例。 该电路包括存储器阵列，该存储器阵列包括多个修整位单元，以在IC通电之后存储并提供修整位以修剪IC的主电路中的寄存器。 存储器阵列还包括复制位电路以产生多个复制位。 耦合到存储器阵列和IC的主电路的逻辑电路被配置为接收复制位，并且向IC提供指示修剪位何时有效的信号。 在一个实施例中，电路还包括冗余校验逻辑，其被配置为从存储器阵列接收多个修剪位，将修整位的数目与预定或计算的值进行比较，并向逻辑电路提供BITS_OK信号 。

公开(公告)号：US08225264B2

公开(公告)日：2012-07-17

申请号：US12583545

申请日：2009-08-21

申请人： Steven Huynh ,  David Kunst

发明人： Steven Huynh ,  David Kunst

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L2224/49171 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

公开(公告)号：US08102676B2

公开(公告)日：2012-01-24

申请号：US12927940

申请日：2010-11-29

申请人： Steven Huynh ,  Matthew Grant ,  David Kunst ,  Zhibo Tao

发明人： Steven Huynh ,  Matthew Grant ,  David Kunst ,  Zhibo Tao

IPC分类号： H02M3/335

CPC分类号： H02M3/33523

摘要： A cord correction circuit in a primary-side-controlled flyback converter compensates for the loss of output voltage caused by the resistance of the charger cord. In one embodiment, a correction voltage is subtracted from a feedback voltage received from a primary-side auxiliary inductor. A pre-amplifier then compares a reference voltage to the corrected feedback voltage. In another embodiment, the correction voltage is summed with the reference voltage, and the pre-amplifier compares the feedback voltage to the corrected reference voltage. The difference between the voltages on the input leads of the pre-amplifier is used to increase the output voltage to compensate for the voltage lost through the charger cord. The flyback converter also has a comparing circuit and a control loop that maintain the peak level of current flowing through the primary inductor of the converter. Adjusting the frequency and pulse width of an inductor switch signal controls the converter output current.

摘要翻译： 初级侧控制反激转换器中的电线校正电路补偿由充电器线的电阻引起的输出电压的损失。 在一个实施例中，从从初级侧辅助电感器接收的反馈电压中减去校正电压。 然后，前置放大器将参考电压与校正的反馈电压进行比较。 在另一个实施例中，校正电压与参考电压相加，并且前置放大器将反馈电压与校正的参考电压进行比较。 前置放大器的输入引脚上的电压之间的差异用于增加输出电压以补偿通过充电器线损失的电压。 反激转换器还具有比较电路和控制回路，其保持流经转换器初级电感器的电流的峰值电平。 调整电感开关信号的频率和脉冲宽度可控制转换器的输出电流。

公开(公告)号：US20090319975A1

公开(公告)日：2009-12-24

申请号：US12583706

申请日：2009-08-25

申请人： Steven Huynh ,  David Kunst

发明人： Steven Huynh ,  David Kunst

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L2224/49171 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

公开(公告)号：US20080259654A1

公开(公告)日：2008-10-23

申请号：US11897131

申请日：2007-08-28

申请人： Steven Huynh ,  Matthew Grant ,  David Kunst ,  Zhibo Tao

发明人： Steven Huynh ,  Matthew Grant ,  David Kunst ,  Zhibo Tao

IPC分类号： H02M3/335

CPC分类号： H02M3/33523

摘要： A cord correction circuit in a primary-side-controlled flyback converter compensates for the loss of output voltage caused by the resistance of the charger cord. In one embodiment, a correction voltage is subtracted from a feedback voltage received from a primary-side auxiliary inductor. A pre-amplifier then compares a reference voltage to the corrected feedback voltage. In another embodiment, the correction voltage is summed with the reference voltage, and the pre-amplifier compares the feedback voltage to the corrected reference voltage. The difference between the voltages on the input leads of the pre-amplifier is used to increase the output voltage to compensate for the voltage lost through the charger cord. The flyback converter also has a comparing circuit and a control loop that maintain the peak level of current flowing through the primary inductor of the converter. Adjusting the frequency and pulse width of an inductor switch signal controls the converter output current.

摘要翻译： 初级侧控制反激转换器中的电线校正电路补偿由充电器线的电阻引起的输出电压的损失。 在一个实施例中，从从初级侧辅助电感器接收的反馈电压中减去校正电压。 然后，前置放大器将参考电压与校正的反馈电压进行比较。 在另一个实施例中，校正电压与参考电压相加，并且前置放大器将反馈电压与校正的参考电压进行比较。 前置放大器的输入引脚上的电压之间的差异用于增加输出电压以补偿通过充电器线损失的电压。 反激转换器还具有比较电路和控制回路，其保持流经转换器初级电感器的电流的峰值电平。 调整电感开关信号的频率和脉冲宽度可控制转换器的输出电流。

公开(公告)号：US20080192515A1

公开(公告)日：2008-08-14

申请号：US11789160

申请日：2007-04-23

申请人： Steven Huynh ,  Matthew Grant ,  David Kunst ,  Zhibo Tao

发明人： Steven Huynh ,  Matthew Grant ,  David Kunst ,  Zhibo Tao

IPC分类号： H02M3/335

CPC分类号： H02M3/33507 ,  H02M3/33523 ,  H02M2001/0009

摘要： A comparing circuit and a control loop are used to maintain the peak level of current flowing through an inductor of a flyback converter. An inductor switch control signal controls an inductor switch through which the inductor current flows. The inductor current increases at a ramp-up rate during a ramp time and stops increasing at the end of the ramp time. The comparing circuit generates a timing signal that indicates a target time at which the inductor current would reach a predetermined current limit if the inductor current continued to increase at the ramp-up rate. The control loop then receives the timing signal and compares the target time to the end of the ramp time. The pulse width of the inductor switch control signal is increased when the target time occurs after the end of the ramp time. Adjusting the pulse width controls the peak of the inductor current.

摘要翻译： 使用比较电路和控制回路来保持流过反激式转换器的电感器的电流的峰值电平。 电感开关控制信号控制电感电流流过的电感开关。 电感电流在斜坡时间内以斜升速率增加，并在斜坡时间结束时停止增加。 比较电路产生一个定时信号，其指示如果电感器电流以升高速率继续增加，则电感器电流将达到预定电流极限的目标时间。 然后，控制环路接收定时信号，并将目标时间与斜坡时间结束进行比较。 当斜坡时间结束后，当目标时间发生时，电感开关控制信号的脉冲宽度就会增加。 调整脉冲宽度可以控制电感电流的峰值。

公开(公告)号：US20080086710A1

公开(公告)日：2008-04-10

申请号：US11544876

申请日：2006-10-07

申请人： Steven Huynh ,  David Kunst

发明人： Steven Huynh ,  David Kunst

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L2224/49171 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end-application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard-IC fabrication process. In many implementations, the physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

摘要翻译： 提供了一种集成电路（IC）及其制造方法，其包括以下步骤：指定适合于特定终端应用的多个所需的瓦片模块，每个模块化瓦片被配置为执行预定功能并被构造为具有大约 长度和宽度相同的尺寸。 模块化瓦片用于在标准IC制造工艺中形成IC。 在许多实现中，IC的物理布局不包括路由的步骤。 能力还包括配置模块化瓦片以具有可编程的性能参数，并且配置模块化瓦片，以便基于可编程参数彼此有用地进行协调。

公开(公告)号：US20080083936A1

公开(公告)日：2008-04-10

申请号：US11978319

申请日：2007-10-29

申请人： Steven Huynh ,  David Kunst

发明人： Steven Huynh ,  David Kunst

IPC分类号： H01L27/10 ,  G06F17/50

CPC分类号： G06F17/5072 ,  H01L2224/49171

摘要： A method of constructing an integrated circuit involves selecting modular tiles and then generating a functional circuit layout using the tiles. Modular tiles that perform predetermined functions and that have approximately the same length and width dimensions are selected from a library of validated tiles. The tiles have input-output terminals embedded in their upper active layers. A functional circuit layout for the integrated circuit is generated using the tiles. In many implementations, the physical layout of the integrated circuit does not include the step of routing. Then an interconnect layer is added over the functional circuitry of the tiles and connects the input-output terminals to bond pads located at the perimeter of the functional circuit layout. Chip data corresponding to the functional circuit layout is generated, and then mask reticles corresponding to the chip data are generated. The integrated circuit is formed on a wafer based on the mask reticles.

摘要翻译： 构成集成电路的方法涉及选择模块化瓦片，然后使用瓦片生成功能电路布局。 执行预定功能并且具有大致相同的长度和宽度尺寸的模块化瓷砖从经验证的瓦片库中选择。 瓦片具有嵌入其上活性层中的输入 - 输出端子。 使用瓦片生成集成电路的功能电路布局。 在许多实现中，集成电路的物理布局不包括路由步骤。 然后在瓦片的功能电路上添加互连层，并将输入 - 输出端子连接到位于功能电路布局的周边的接合焊盘。 产生与功能电路布局相对应的芯片数据，然后产生对应于芯片数据的掩模。 集成电路基于掩模标线形成在晶片上。

公开(公告)号：US09141748B2

公开(公告)日：2015-09-22

申请号：US12583552

申请日：2009-08-21

申请人： Steven Huynh ,  David Kunst

发明人： Steven Huynh ,  David Kunst

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  H01L2224/49171 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter.

公开(公告)号：US07961483B2

公开(公告)日：2011-06-14

申请号：US12386609

申请日：2009-04-20

申请人： Steven Huynh ,  Matthew Grant ,  David Kunst ,  Zhibo Tao

发明人： Steven Huynh ,  Matthew Grant ,  David Kunst ,  Zhibo Tao

IPC分类号： H02M3/335

CPC分类号： H02M3/33507 ,  H02M3/33523 ,  H02M2001/0009

摘要： A comparing circuit and a control loop are used to maintain the peak level of current flowing through an inductor of a flyback converter. An inductor switch control signal controls an inductor switch through which the inductor current flows. The inductor current increases at a ramp-up rate during a ramp time and stops increasing at the end of the ramp time. The comparing circuit generates a timing signal that indicates a target time at which the inductor current would reach a predetermined current limit if the inductor current continued to increase at the ramp-up rate. The control loop then receives the timing signal and compares the target time to the end of the ramp time. The pulse width of the inductor switch control signal is increased when the target time occurs after the end of the ramp time. Adjusting the pulse width controls the peak of the inductor current.

摘要翻译： 使用比较电路和控制回路来保持流过反激式转换器的电感器的电流的峰值电平。 电感开关控制信号控制电感电流流过的电感开关。 电感电流在斜坡时间内以斜升速率增加，并在斜坡时间结束时停止增加。 比较电路产生一个定时信号，其指示如果电感器电流以升高速率继续增加，则电感器电流将达到预定电流极限的目标时间。 然后，控制环路接收定时信号，并将目标时间与斜坡时间结束进行比较。 当斜坡时间结束后，当目标时间发生时，电感开关控制信号的脉冲宽度就会增加。 调整脉冲宽度可以控制电感电流的峰值。