公开(公告)号：US20080282210A1

公开(公告)日：2008-11-13

申请号：US12119862

申请日：2008-05-13

Applicant: Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

Inventor： Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

Abstract translation: 用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。 表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。 产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。 提取引擎从提出的产品布局中提取预定的布局属性。 在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。 然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

公开(公告)号：US07356800B2

公开(公告)日：2008-04-08

申请号：US11503323

申请日：2006-08-10

Applicant: Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

Inventor： Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

公开(公告)号：US07373625B2

公开(公告)日：2008-05-13

申请号：US11503433

申请日：2006-08-10

Applicant: Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

Inventor： Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

Abstract translation: 用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。 表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。 产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。 提取引擎从提出的产品布局中提取预定的布局属性。 在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。 然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

公开(公告)号：US07174521B2

公开(公告)日：2007-02-06

申请号：US11078630

申请日：2005-03-10

Applicant: Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

Inventor： Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

公开(公告)号：US06901564B2

公开(公告)日：2005-05-31

申请号：US10200045

申请日：2002-07-18

Applicant: Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

Inventor： Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

IPC: H01L21/00 ,  G01R31/26 ,  G05B15/02 ,  H01L21/02 ,  H01L21/66 ,  H01L23/544 ,  G06F17/50 ,  G06F19/00

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A yield for an integrated circuit is predicted by processing a wafer to have a portion fabricated with at least one layout attribute of the integrated circuit. The portion of the wafer is analyzed to determine an actual yield associated with the at least one layout attribute. A systematic yield associated with the at least one layout attribute is determined based on the actual yield and a predicted yield associated with the at least one layout attribute. The predicted yield assumes that random defects are the only yield loss mechanism. A yield of an actual or proprosed product layout is predicted for the integrated circuit based on the systematic yield.

Abstract translation: 通过处理晶片以使具有集成电路的至少一个布局属性制造的部分来预测集成电路的产量。 分析晶片的部分以确定与至少一个布局属性相关联的实际屈服。 基于实际产量和与至少一个布局属性相关联的预测收益来确定与所述至少一个布局属性相关联的系统收益。 预测产量假设随机缺陷是唯一的产量损失机制。 基于系统产量预测集成电路的实际或推动产品布局的产量。

公开(公告)号：US07673262B2

公开(公告)日：2010-03-02

申请号：US12119862

申请日：2008-05-13

Applicant: Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

Inventor： Brian E. Stine ,  Christopher Hess ,  John Kibarian ,  Kimon Michaels ,  Joseph C. Davis ,  Purnendu K. Mozumder ,  Sherry F. Lee ,  Larg H. Weiland ,  Dennis J. Ciplickas ,  David M. Stashower

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G05B15/02 ,  H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes at least one type of characterization vehicle which incorporates at least one feature which is representative of at least one type of feature to be incorporated in the final integrated circuit product. The characterization vehicle is subjected to at least one of the process operations making up the fabrication cycle to be used in fabricating the integrated circuit product in order to produce a yield model. The yield model embodies a layout as defined by the characterization vehicle and preferably includes features which facilitate the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine extracts predetermined layout attributes from a proposed product layout. Operating on the yield model, the extraction engine produces yield predictions as a function of layout attributes and broken down by layers or steps in the fabrication process. These yield predictions are then used to determine which areas in the fabrication process require the most improvement.

Abstract translation: 用于预测集成电路的产量的系统和方法包括至少一种表征车辆，其包括至少一个特征，其代表要并入到最终集成电路产品中的至少一种类型的特征。 表征车辆经受构成制造周期的工艺操作中的至少一个，以用于制造集成电路产品以产生屈服模型。 产量模型体现了由表征车辆定义的布局，并且优选地包括便于在运行速度下收集电测试数据和测试原型部分的特征。 提取引擎从提出的产品布局中提取预定的布局属性。 在产量模型上运行，提取引擎作为布局属性的函数产生产量预测，并在制造过程中按层或步骤细分。 然后使用这些产量预测来确定制造过程中哪些领域需要最大的改进。

公开(公告)号：US06795952B1

公开(公告)日：2004-09-21

申请号：US10130448

申请日：2002-11-20

Applicant: Brian E. Stine ,  David M. Stashower ,  Sherry F. Lee ,  Kurt H. Weiner

Inventor： Brian E. Stine ,  David M. Stashower ,  Sherry F. Lee ,  Kurt H. Weiner

IPC: G06F945

CPC classification number: H01L22/20 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system and method for predicting yield of integrated circuits includes a characterization vehicle (12) having at least one feature representative of at least one type of feature to be incorporated in the final integrated circuit, preferably a device neighborhood, process neighborhood characterization vehicle. The characterization vehicle (12) is subjected to process operations making up the fabrication cycle to be used in fabricating the integrated circuit in order to produce a yield model (16). The yield model (16) embodies a layout as defined by the characterization vehicle (12) and preferably includes features which facilitates the gathering of electrical test data and testing of prototype sections at operating speeds. An extraction engine (18) extracts predetermined layout attributes (26) from a proposed product layout (20). Operating on the yield model, the extraction engine (18) produces yield predictions (22) as a function of layout attributes (26) and broken down by layers or steps in the fabrication process (14).

Abstract translation: 用于预测集成电路的产量的系统和方法包括具有至少一个特征的表征车辆（12），该至少一个特征表示要并入到最终集成电路中的至少一种类型的特征，优选地是装置邻域，过程邻域表征车辆。 表征车辆（12）经过组成制造周期的工艺操作，以用于制造集成电路，以便产生屈服模型（16）。 产量模型（16）体现了由表征车辆（12）定义的布局，并且优选地包括有助于在运行速度下收集电测试数据和测试原型部分的特征。 提取引擎（18）从提出的产品布局（20）中提取预定的布局属性（26）。 在产量模型上操作，提取引擎（18）根据布局属性（26）产生产量预测（22），并在制造过程（14）中按层或步骤细分。