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公开(公告)号：US06674654B2
公开(公告)日：2004-01-06
申请号：US10108940
申请日：2002-03-27
IPC分类号： H02M3335
CPC分类号： H02M3/158 , H02M3/3372
摘要： A DC—DC voltage converter has a controller, two switches, a transformer and two rectifying diodes. The transformer has a first winding, a second winding and a center tap. Input voltage is connected between the center tap and ground. An anode of each diode is connected to the outer ends of the two windings and the cathodes of the two diodes are connected together to provide a positive output with respect to ground. Each switch is connected between an outer end of one winding and ground. The controller generates control signals to turn the switches on and off for limited periods of time in phase opposition to alternately connect the outer ends of the first and second winding to ground to cause current to flow alternatively in one of the windings and induce a voltage in the other winding that is additive to the input voltage, thereby providing an output voltage greater than the input voltage. The converter provides stable operation with good voltage regulation over a wide range of load conditions without the use of feedback.
摘要翻译： DC-DC电压转换器有一个控制器，两个开关，一个变压器和两个整流二极管。 变压器具有第一绕组，第二绕组和中心抽头。 输入电压连接在中心抽头和地之间。 每个二极管的阳极连接到两个绕组的外端，并且两个二极管的阴极连接在一起，以提供相对于地的正输出。 每个开关连接在一个绕组的外端和地之间。 控制器产生控制信号，以在相位相反的有限时间段内打开和关闭开关，以交替地将第一和第二绕组的外端连接到地，以使电流在一个绕组中交替地流动，并且在 另一绕组，其与输入电压相加，从而提供大于输入电压的输出电压。 该转换器在宽范围的负载条件下提供稳定的运行，具有良好的电压调节，无需使用反馈。
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公开(公告)号：US06954929B2
公开(公告)日：2005-10-11
申请号：US09917982
申请日：2001-07-30
CPC分类号： G06F8/63
摘要： The invention provides a method of implementing firmware updates to programmable parts within circuit boards on a manufacturing line. An image file of firmware for each of the parts is created and stored on a firmware server. The programmable parts are preferably integrated with the printed circuit boards; each of the boards networks to the firmware server by connection with an interface server, such that the image files download to the circuit board for programming the board's internal programmable parts. Networking between the parts and the firmware server can include communications across the Internet and/or one or more area networks. Multiple interface servers may be integral with the products incorporating the programmable parts so that many products may be updated concurrently.
摘要翻译： 本发明提供了一种对生产线上的电路板内的可编程部件实施固件更新的方法。 创建每个部件的固件的映像文件并将其存储在固件服务器上。 可编程部件优选地与印刷电路板集成; 每个板通过与接口服务器的连接网络连接到固件服务器，使得图像文件下载到电路板以编程板的内部可编程部件。 部件和固件服务器之间的联网可以包括通过因特网和/或一个或多个区域网络的通信。 多个接口服务器可能与包含可编程部件的产品集成在一起，从而可以同时更新许多产品。
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3.发明授权Method for accessing scan chains and updating EEPROM-resident FPGA code through a system management processor and JTAG bus 有权通过系统管理处理器和JTAG总线访问扫描链和更新EEPROM驻留的FPGA代码的方法公开(公告)号：US06883109B2
公开(公告)日：2005-04-19
申请号：US09918030
申请日：2001-07-30
IPC分类号： G06F11/00 , G01R31/3185 , G06F9/24 , G06F9/38 , G06F17/50
CPC分类号： G01R31/318558 , G06F9/24 , G06F9/3861 , G06F17/5054
摘要： A method of updating programmable device configuration code stored in EEPROMs of a system is operable on complex systems having separate management and system processors. The method includes executing a sequence for updating programmable device configuration code on a management processor of the system including erasing the EEPROMs, writing at least one block of configuration code to the EEPROMs, and checking for errors after writing. The errors checked for include failure of a FIFO to empty. Upon detecting errors, the method includes automatically retrying writes. Embodiments of the method are operable on systems having multiple serial busses interconnecting EEPROMs to a common configuration logic, and on systems having multiple management processors each capable of accessing the common configuration logic.
摘要翻译： 存储在系统的EEPROM中的可更新可编程设备配置码的方法可在具有独立管理和系统处理器的复杂系统上操作。 该方法包括执行用于在系统的管理处理器上更新可编程设备配置代码的序列，包括擦除EEPROM，将至少一个配置代码块写入EEPROM，以及在写入后检查错误。 检查的错误包括FIFO清空的故障。 在检测到错误时，该方法包括自动重试写入。 该方法的实施例可用于具有将EEPROM互连到公共配置逻辑的多个串行总线的系统，以及具有多个能够访问公共配置逻辑的多个管理处理器的系统。
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公开(公告)号：US07676621B2
公开(公告)日：2010-03-09
申请号：US10662034
申请日：2003-09-12
IPC分类号： G06F13/14
CPC分类号： G06F13/4282 , G06F2213/0016
摘要： A computer system is disclosed that includes: a communications bus implemented in accordance with an Inter-IC bus specification; a bus controller coupled to the communications bus; a send machine coupled between a host processor and the bus controller; and a first-in first-out (FIFO) buffer coupled to the send machine and coupled between the host processor and the bus controller.
摘要翻译： 公开了一种计算机系统，其包括：根据IC间总线规范实现的通信总线; 耦合到通信总线的总线控制器; 耦合在主处理器和总线控制器之间的发送机; 以及耦合到发送机并且耦合在主处理器和总线控制器之间的先进先出（FIFO）缓冲器。
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5.发明授权Apparatus and method for selectively mapping proper boot image to processors of heterogeneous computer systems 有权用于选择性地将适当引导映像映射到异构计算机系统的处理器的装置和方法公开(公告)号：US07363484B2
公开(公告)日：2008-04-22
申请号：US10662563
申请日：2003-09-15
申请人： Michael Ryan Davis , Russ William Herrell , David R. Maciorowski , Paul J. Mantey , Michael D. Young , Danial V. Zilavy
发明人： Michael Ryan Davis , Russ William Herrell , David R. Maciorowski , Paul J. Mantey , Michael D. Young , Danial V. Zilavy
IPC分类号： G06F9/00 , G06F15/177 , G06F9/45
CPC分类号： G06F15/177 , G06F9/4405
摘要： A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.
摘要翻译： 在蜂窝计算机系统的每个小区上提供机器可读标识寄存器。 在系统启动期间读取识别寄存器以识别处理器类型，其可以包括与该单元相关联的指令集体系结构（ISA）。 处理器类型信息用于确保向单元的处理器提供兼容的引导映像。 在另一个实施例中，系统管理子系统具有版本选择标志。 当版本选择标志处于第一状态时，提供给单元的处理器的兼容引导映像是当前引导映像; 其中选择标志处于第二状态，提供给单元的处理器的兼容引导映像是引导映像的旧版本。
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6.发明授权公开(公告)号：US07200781B2
公开(公告)日：2007-04-03
申请号：US10437981
申请日：2003-05-14
IPC分类号： G06F11/00
CPC分类号： G06F11/0745 , G06F11/0757
摘要： Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.
摘要翻译： 公开了用于检测和响应通过总线收发器耦合到通信总线的主机的故障的技术和装置。
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公开(公告)号：US07039736B2
公开(公告)日：2006-05-02
申请号：US10342886
申请日：2003-01-15
IPC分类号： G06F13/36 , G06F13/368 , G06F12/00 , G06F13/00 , G06F11/00
CPC分类号： G06F13/4031
摘要： Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.
摘要翻译： 公开了用于提供对总线主控系统资源的访问的系统和方法，包括在第一总线和总线访问仲裁器之间布置总线多路复用器，其中第一总线耦合到至少一个系统资源，总线访问由总线仲裁 访问仲裁器，并且控制总线多路复用器将第二总线耦合到第一总线，从而在第一总线和绕过总线访问仲裁器的第二总线之间提供链路。
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公开(公告)号：US06404176B1
公开(公告)日：2002-06-11
申请号：US09919123
申请日：2001-07-31
IPC分类号： G05F304
CPC分类号： H02M3/158 , H02M3/3372
摘要： A DC-DC voltage converter comprises a controller, two switches, a transformer and two rectifying diodes. The transformer has a first winding, a second winding and a center tap. Input voltage in connected between the center tap and ground. An anode of each diode is connected to the outer ends of the two windings and the cathodes of the two diodes are connected together to provide a positive output with respect to ground. Each switch is connected between an outer end of one windings and ground. The controller generates control signals to turn the switches on and off for limited periods of time in phase opposition to alternately connect the outer ends of the first and second winding to ground to cause current to flow alternatively in one of the windings and induce a voltage in the other winding that is additive to the input voltage, thereby providing an output voltage greater than the input voltage. The converter provides stable operation with good voltage regulation over a wide range of load conditions without the use of feedback.
摘要翻译： DC-DC电压转换器包括一个控制器，两个开关，一个变压器和两个整流二极管。 变压器具有第一绕组，第二绕组和中心抽头。 连接中心龙头和地面之间的输入电压。 每个二极管的阳极连接到两个绕组的外端，并且两个二极管的阴极连接在一起，以提供相对于地的正输出。 每个开关连接在一个绕组的外端和地之间。 控制器产生控制信号，以在相位相反的有限时间段内打开和关闭开关，以交替地将第一和第二绕组的外端连接到地，以使电流在一个绕组中交替地流动，并且在 另一绕组，其与输入电压相加，从而提供大于输入电压的输出电压。 该转换器在宽范围的负载条件下提供稳定的运行，具有良好的电压调节，无需使用反馈。
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9.发明授权Systems-events core for monitorings system events for a cellular computer system within a parent computer system, system-event manager for monitoring system events for more than one cellular computer system, and related system and method 失效用于监视父计算机系统内的蜂窝计算机系统的系统事件核心，用于监视多于一个蜂窝计算机系统的系统事件的系统事件管理器以及相关系统和方法公开(公告)号：US07197587B2
公开(公告)日：2007-03-27
申请号：US10176211
申请日：2002-06-19
IPC分类号： G06F13/24
CPC分类号： G06F9/4812 , G06F13/24
摘要： A system-event core for monitoring system events in a cellular computer system within a parent computer system is provided. The system-event core comprises: a control register block for each cell computer system configured to mask one or more system events and configurable to be masked by a system-event manager, an input/output block operable to communicate with a computer bus, a register block operable to store data about system events, and interrupt generation logic operable to control interrupts for the cellular computer system.
摘要翻译： 提供了一种用于在父计算机系统内的蜂窝计算机系统中监视系统事件的系统事件核心。 系统事件核心包括：用于每个小区计算机系统的控制寄存器块，被配置为屏蔽一个或多个系统事件并且可配置为被系统事件管理器屏蔽，可操作以与计算机总线通信的输入/输出块， 寄存器块，用于存储关于系统事件的数据，以及中断产生逻辑，可操作以控制蜂窝计算机系统的中断。
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公开(公告)号：US06914951B2
公开(公告)日：2005-07-05
申请号：US09912191
申请日：2001-07-24
IPC分类号： H03K5/1252 , H04B1/10
CPC分类号： H03K5/1252
摘要： Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.
摘要翻译： 逻辑设备将信号线上的噪声信号滤波到数字电路。 边缘检测器确定相对于快速时钟的噪声信号的一个或多个边缘。 指示边沿的信号异步复位定时器; 当信号线稳定时，定时器对信号线的锁存器进行计时，并且在由慢时钟限定的时间段内没有由边缘检测器检测到噪声信号。 慢时钟比快时钟慢几个数量级。 边缘检测器可以由一个触发器和XOR门构成。 当定时器计时时，第二触发器耦合到信号线和定时器的输出，以将信号线的锁存值传递到数字电路。
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