公开(公告)号：US20110057736A1

公开(公告)日：2011-03-10

申请号：US12944839

申请日：2010-11-12

申请人： Dean A. Badillo

发明人： Dean A. Badillo

IPC分类号： H03K3/03

CPC分类号： H03K3/0315

摘要： In a voltage-controlled ring oscillator, one or more controllable current sources generate a bias current in response to a tuning voltage. Any of several features can be included to promote frequency tuning linearity. In accordance with one feature, the ring oscillator circuit transistors can be sized relative to one another to skew the rise and fall times of the ring oscillator output signal with respect to one another. In accordance with another feature, a peak limiter can limit the oscillation amplitude in response to the bias current. In accordance with still another feature, a controllable bias current source can include a voltage-to-current converter and one or more groups of digitally controlled current source transistors.

摘要翻译： 在压控环形振荡器中，响应于调谐电压，一个或多个可控电流源产生偏置电流。 可以包括几个功能中的任何一个来提升频率调谐线性度。 根据一个特征，环形振荡器电路晶体管可以相对于彼此来确定尺寸，以扭曲环形振荡器输出信号相对于彼此的上升和下降时间。 根据另一特征，峰值限制器可以响应于偏置电流来限制振荡幅度。 根据另一个特征，可控偏置电流源可以包括电压 - 电流转换器和一组或多组数字控制的电流源晶体管。

公开(公告)号：US20130106473A1

公开(公告)日：2013-05-02

申请号：US13281921

申请日：2011-10-26

申请人： Bruce M. Newman ,  Dean A. Badillo ,  Reimund Rebel ,  Klaus Juergen Schoepf ,  Mohammad Asmani

发明人： Bruce M. Newman ,  Dean A. Badillo ,  Reimund Rebel ,  Klaus Juergen Schoepf ,  Mohammad Asmani

IPC分类号： H03L7/00

CPC分类号： H03L5/00 ,  H03K17/223

摘要： The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.

摘要翻译： 所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。 所公开的电路包括触发器电路和第一比较器电路。 根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。 第一比较器电路输出时钟信号，其中触发电路由时钟信号计时。 触发电路的Q输出节点提供上电复位信号，当供电电压处于小于触发电压电平Vtrig的电压电平时，上电复位信号处于LO状态。 当电源电压处于大于触发电压电平Vtrig的电压电平时，上电复位信号处于HI状态。

公开(公告)号：US08415993B1

公开(公告)日：2013-04-09

申请号：US13281921

申请日：2011-10-26

申请人： Bruce M. Newman ,  Dean A. Badillo ,  Reimund Rebel ,  Klaus Juergen Schoepf ,  Mohammad Asmani

发明人： Bruce M. Newman ,  Dean A. Badillo ,  Reimund Rebel ,  Klaus Juergen Schoepf ,  Mohammad Asmani

IPC分类号： H03L7/00

CPC分类号： H03L5/00 ,  H03K17/223

摘要： The disclosed power-on reset circuit provides an indication of when and whether a supply voltage Vdd has reached a trigger voltage level Vtrig. The disclosed circuit includes a flip-flop circuit and a first comparator circuit. The circuit according to the invention has a D input node of the flip-flop circuit coupled to the supply voltage. The first comparator circuit outputs a clock signal, where the flip-flop circuit is clocked by the clock signal. A Q output node of the flip-flop circuit provides the power-on reset signal, where the power-on reset signal is in a LO state when the supply voltage is at a voltage level that is less than the trigger voltage level Vtrig. The power-on reset signal is in a HI state when the supply voltage is at a voltage level that is greater than the trigger voltage level Vtrig.

摘要翻译： 所公开的上电复位电路提供电源电压Vdd何时以及是否达到触发电压电平Vtrig的指示。 所公开的电路包括触发器电路和第一比较器电路。 根据本发明的电路具有耦合到电源电压的触发器电路的D输入节点。 第一比较器电路输出时钟信号，其中触发电路由时钟信号计时。 触发电路的Q输出节点提供上电复位信号，当供电电压处于小于触发电压电平Vtrig的电压电平时，上电复位信号处于LO状态。 当电源电压处于大于触发电压电平Vtrig的电压电平时，上电复位信号处于HI状态。

公开(公告)号：US08395456B2

公开(公告)日：2013-03-12

申请号：US13049738

申请日：2011-03-16

申请人： Dean A. Badillo ,  Reimund Rebel ,  Klaus Juergen Schoepf

发明人： Dean A. Badillo ,  Reimund Rebel ,  Klaus Juergen Schoepf

IPC分类号： H03B5/30

CPC分类号： H03G3/004 ,  H03B5/30 ,  H03F3/45071 ,  H03H11/22

摘要： A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair.

摘要翻译： 公开了一种可变相位放大器电路及其在具有谐振器的调谐装置中的使用方法。 可变相位放大器接收输入差分信号对。 输入差分信号对可以由谐振器装置产生。 响应于接收到输入差分信号对，可变相位放大器产生修正的差分信号对。 可变相位放大器提供了以准确和稳定的方式改变修改的差分信号对相对于输入差分信号对的相位的装置。 如果将其中引入的相移的修正的差分信号对反馈到谐振器装置，则谐振器将改变其振荡频率，其中新的振荡频率是修改的差分信号对的相位的函数。

公开(公告)号：US20120268169A1

公开(公告)日：2012-10-25

申请号：US13089859

申请日：2011-04-19

申请人： Dean A. Badillo ,  David R. LoCascio

发明人： Dean A. Badillo ,  David R. LoCascio

IPC分类号： H02M11/00 ,  H03F3/45

CPC分类号： G05F5/00 ,  H03F1/301 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2203/45654

摘要： A differential current signal circuit is described which includes a voltage to differential current converter circuit that generates a differential pair of current output signals in response to receiving a voltage input signal, where the differential pair of current output signals are linearly proportional to the voltage input signal within a voltage operating range from a minimum operating voltage to a maximum operating voltage. The differential pair of current output signals are linear over a wide range of voltage input signals. A correction circuit is included which eliminates voltage offsets in the voltage operating range due to process and temperature variations. The correction circuit also provides the capability to adjust the minimum operating voltage, and eliminates variations in the minimum operating voltage due to process and temperature variations.

摘要翻译： 描述了一种差分电流信号电路，其包括对差分电流转换器电路的电压，其响应于接收电压输入信号而产生电流输出信号的差分对，其中电流输出信号的差分对与电压输入信号成线性比例 在从最小工作电压到最大工作电压的电压工作范围内。 电流输出信号的差分对在宽范围的电压输入信号上是线性的。 包括校正电路，其消除了由于过程和温度变化引起的电压工作范围内的电压偏移。 校正电路还提供调整最小工作电压的能力，并消除由于工艺和温度变化引起的最小工作电压的变化。

公开(公告)号：US20110163819A1

公开(公告)日：2011-07-07

申请号：US13049738

申请日：2011-03-16

申请人： Dean A. Badillo ,  Reimund Rebel ,  Klaus Juergen Schoepf

发明人： Dean A. Badillo ,  Reimund Rebel ,  Klaus Juergen Schoepf

IPC分类号： H03B5/24 ,  H03H11/20

CPC分类号： H03G3/004 ,  H03B5/30 ,  H03F3/45071 ,  H03H11/22

摘要： A variable phase amplifier circuit is disclosed and its method of use in tuning devices having resonators. The variable phase amplifier receives an input differential signal pair. The input differential signal pair can be generated by a resonator device. The variable phase amplifier generates a modified differential signal pair in response to receiving the input differential signal pair. The variable phase amplifier provides a means to vary the phase of the modified differential signal pair with respect to the input differential signal pair, in an accurate and stable manner. If the modified differential signal pair with a phase shift introduced in it is fed back to the resonator device, the resonator will change its frequency of oscillation, where the new frequency of oscillation is a function of the phase of the modified differential signal pair.

摘要翻译： 公开了一种可变相位放大器电路及其在具有谐振器的调谐装置中的使用方法。 可变相位放大器接收输入差分信号对。 输入差分信号对可以由谐振器装置产生。 响应于接收到输入差分信号对，可变相位放大器产生修正的差分信号对。 可变相位放大器提供了以准确和稳定的方式改变修改的差分信号对相对于输入差分信号对的相位的装置。 如果将其中引入的相移的修正的差分信号对反馈到谐振器装置，则谐振器将改变其振荡频率，其中新的振荡频率是修改的差分信号对的相位的函数。

公开(公告)号：US08633739B2

公开(公告)日：2014-01-21

申请号：US13169994

申请日：2011-06-27

申请人： Dean A. Badillo

发明人： Dean A. Badillo

IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00

CPC分类号： H03K23/667 ,  H03K23/68

摘要： Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle.

摘要翻译： 通过依次选择用于除法的相位信号进行分数分频，其中不仅响应于分频的前一相位信号，而且响应于相位信号中的第二相位信号，从而从先前相位信号转换到下一相位信号进行分频。 至少部分响应于具有相对于下一个相位信号的相位较大的相位（相对于相位信号序列）的相位的第二相位信号触发的相位转移可以帮助信号毛刺的最小化。 可以将第一分频信号进一步分割以产生具有50％占空比的第二分频信号。

公开(公告)号：US08441288B2

公开(公告)日：2013-05-14

申请号：US13089859

申请日：2011-04-19

申请人： Dean A. Badillo ,  David R. LoCascio

发明人： Dean A. Badillo ,  David R. LoCascio

IPC分类号： H02M11/00

CPC分类号： G05F5/00 ,  H03F1/301 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2203/45654

摘要： A differential current signal circuit is described which includes a voltage to differential current converter circuit that generates a differential pair of current output signals in response to receiving a voltage input signal, where the differential pair of current output signals are linearly proportional to the voltage input signal within a voltage operating range from a minimum operating voltage to a maximum operating voltage. The differential pair of current output signals are linear over a wide range of voltage input signals. A correction circuit is included which eliminates voltage offsets in the voltage operating range due to process and temperature variations. The correction circuit also provides the capability to adjust the minimum operating voltage, and eliminates variations in the minimum operating voltage due to process and temperature variations.

摘要翻译： 描述了一种差分电流信号电路，其包括对差分电流转换器电路的电压，其响应于接收电压输入信号而产生电流输出信号的差分对，其中电流输出信号的差分对与电压输入信号成线性比例 在从最小工作电压到最大工作电压的电压工作范围内。 电流输出信号的差分对在宽范围的电压输入信号上是线性的。 包括校正电路，其消除了由于过程和温度变化引起的电压工作范围内的电压偏移。 校正电路还提供调整最小工作电压的能力，并消除由于工艺和温度变化引起的最小工作电压的变化。

公开(公告)号：US07969209B2

公开(公告)日：2011-06-28

申请号：US12416736

申请日：2009-04-01

申请人： Dean A. Badillo

发明人： Dean A. Badillo

IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00

CPC分类号： H03K23/667 ,  H03K23/68

摘要： Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle.

摘要翻译： 通过依次选择用于除法的相位信号进行分数分频，其中不仅响应于分频的前一相位信号，而且响应于相位信号中的第二相位信号，从而从先前相位信号转换到下一相位信号进行分频。 至少部分响应于具有相对于下一个相位信号的相位较大的相位（相对于相位信号序列）的相位的第二相位信号触发的相位转移可以帮助信号毛刺的最小化。 可以将第一分频信号进一步分割以产生具有50％占空比的第二分频信号。