公开(公告)号：US08441288B2

公开(公告)日：2013-05-14

申请号：US13089859

申请日：2011-04-19

申请人： Dean A. Badillo ,  David R. LoCascio

发明人： Dean A. Badillo ,  David R. LoCascio

IPC分类号： H02M11/00

CPC分类号： G05F5/00 ,  H03F1/301 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2203/45654

摘要： A differential current signal circuit is described which includes a voltage to differential current converter circuit that generates a differential pair of current output signals in response to receiving a voltage input signal, where the differential pair of current output signals are linearly proportional to the voltage input signal within a voltage operating range from a minimum operating voltage to a maximum operating voltage. The differential pair of current output signals are linear over a wide range of voltage input signals. A correction circuit is included which eliminates voltage offsets in the voltage operating range due to process and temperature variations. The correction circuit also provides the capability to adjust the minimum operating voltage, and eliminates variations in the minimum operating voltage due to process and temperature variations.

摘要翻译： 描述了一种差分电流信号电路，其包括对差分电流转换器电路的电压，其响应于接收电压输入信号而产生电流输出信号的差分对，其中电流输出信号的差分对与电压输入信号成线性比例 在从最小工作电压到最大工作电压的电压工作范围内。 电流输出信号的差分对在宽范围的电压输入信号上是线性的。 包括校正电路，其消除了由于过程和温度变化引起的电压工作范围内的电压偏移。 校正电路还提供调整最小工作电压的能力，并消除由于工艺和温度变化引起的最小工作电压的变化。

公开(公告)号：US20080191919A1

公开(公告)日：2008-08-14

申请号：US11674435

申请日：2007-02-13

申请人： Douglas A. Garrity ,  David R. Locascio

发明人： Douglas A. Garrity ,  David R. Locascio

IPC分类号： H03M1/12

CPC分类号： H03M1/46

摘要： A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.

摘要翻译： 适于将模拟输入信号转换为数字输出信号的A转换器（200）包括用于接收模拟输入信号的模拟输入端（205），耦合到模拟输入端的冗余有符号（RSD）级（210） 和数字部分（220）。 RSD级被配置为在模拟输入端接收模拟输入信号，在第一时钟周期的前半部分期间，从模拟输入信号的数字输出产生第一位数，提供模拟量的残留反馈信号 在第一时钟周期的后半段期间在模拟输入端子处输入信号，并且在第二时钟周期的前半部分期间从剩余反馈信号在数字输出处产生第二数量的位，第二个位数小于 第一位数。

公开(公告)号：US07305642B2

公开(公告)日：2007-12-04

申请号：US11100039

申请日：2005-04-05

申请人： James F. McClellan ,  Patrick G. Drennan ,  Douglas A. Garrity ,  David R. LoCascio ,  Michael J. McGowan

发明人： James F. McClellan ,  Patrick G. Drennan ,  Douglas A. Garrity ,  David R. LoCascio ,  Michael J. McGowan

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5068

摘要： The present invention provides a method for tiling an integrated circuit having a critically matched device such as a transistor. The method obtains an advantage of automatically improving metallic density over critically matched devices thus yielding improved CMP. The method may include the steps of: identifying critically matched devices in the integrated circuit; placing metal tiles over the critically matched device; performing a density test around each critically matched device; and if a density test is not satisfied around a critically matched device, placing at least one metal strip over a critically matched device.

摘要翻译： 本发明提供了一种用于平铺具有诸如晶体管等关键匹配器件的集成电路的方法。 该方法获得了自动提高临界匹配器件的金属密度的优点，从而产生改进的CMP。 该方法可以包括以下步骤：识别集成电路中的严格匹配的设备; 将金属砖放在严格匹配的设备上; 对每个严格匹配的设备进行密度测试; 并且如果在严格匹配的装置周围不能满足密度测试，则将至少一个金属带放置在严格匹配的装置上。

公开(公告)号：US20120268169A1

公开(公告)日：2012-10-25

申请号：US13089859

申请日：2011-04-19

申请人： Dean A. Badillo ,  David R. LoCascio

发明人： Dean A. Badillo ,  David R. LoCascio

IPC分类号： H02M11/00 ,  H03F3/45

CPC分类号： G05F5/00 ,  H03F1/301 ,  H03F3/45183 ,  H03F2200/453 ,  H03F2203/45654

摘要： A differential current signal circuit is described which includes a voltage to differential current converter circuit that generates a differential pair of current output signals in response to receiving a voltage input signal, where the differential pair of current output signals are linearly proportional to the voltage input signal within a voltage operating range from a minimum operating voltage to a maximum operating voltage. The differential pair of current output signals are linear over a wide range of voltage input signals. A correction circuit is included which eliminates voltage offsets in the voltage operating range due to process and temperature variations. The correction circuit also provides the capability to adjust the minimum operating voltage, and eliminates variations in the minimum operating voltage due to process and temperature variations.

摘要翻译： 描述了一种差分电流信号电路，其包括对差分电流转换器电路的电压，其响应于接收电压输入信号而产生电流输出信号的差分对，其中电流输出信号的差分对与电压输入信号成线性比例 在从最小工作电压到最大工作电压的电压工作范围内。 电流输出信号的差分对在宽范围的电压输入信号上是线性的。 包括校正电路，其消除了由于过程和温度变化引起的电压工作范围内的电压偏移。 校正电路还提供调整最小工作电压的能力，并消除由于工艺和温度变化引起的最小工作电压的变化。

公开(公告)号：US20090033371A1

公开(公告)日：2009-02-05

申请号：US12244214

申请日：2008-10-02

申请人： Brandt Braswell ,  David R. LoCascio

发明人： Brandt Braswell ,  David R. LoCascio

IPC分类号： H03K5/22

CPC分类号： G11C27/026

摘要： A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

摘要翻译： 如本文所述的双采样开关电容器架构包括具有对应于两个单独的放大器部分的两个单独输入的放大器。 放大器使用用于第一放大器部分的第一差分晶体管对，用于第二放大器部分的第二差分晶体管对，用于第一差分晶体管对的第一尾电流偏置装置，以及用于第二差分晶体管的第二尾电流偏置装置 对。 尾电流偏置装置由偏置开关结构驱动，交替地激活一个尾电流偏压装置，同时至少部分地去激活另一尾电流偏置装置。 放大器和偏置开关结构协调以消除否则将由单个放大器部分共享的公共寄生电容引起的增益误差。

公开(公告)号：US07305643B2

公开(公告)日：2007-12-04

申请号：US11128659

申请日：2005-05-12

申请人： James F. McClellan ,  Patrick G. Drennan ,  Douglas A. Garrity ,  David R. LoCascio ,  Michael J. McGowan

发明人： James F. McClellan ,  Patrick G. Drennan ,  Douglas A. Garrity ,  David R. LoCascio ,  Michael J. McGowan

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5072 ,  H01L22/20

摘要： A method for placing tiles in an integrated circuit has matched devices that includes the steps of (1) calculating a metal spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (2) calculating a lateral spacing for tiles to be placed adjacent to the matched device in the integrated circuit; (3) placing tiles about the matched device based on the metal spacing and the lateral spacing; (4) performing a density test in an area around the matched device; and (5) if a density test is not satisfied in the area around the matched device, dividing the matched device into at least two subdevices and repeating, with respect to each subdevice, the steps of calculating a metal spacing, calculating a lateral spacing, and placing tiles about each subdevice. The method is further adaptable to various kinds of matched devices including poly resistors, diffused resistors, double-poly capacitors, metal-insulator-metal capacitors, and fringe capacitors.

摘要翻译： 一种用于在集成电路中放置瓦片的方法具有匹配的装置，其包括以下步骤：（1）计算要放置在与集成电路中的匹配装置相邻的瓷砖的金属间隔; （2）计算与所述集成电路中的匹配装置相邻放置的瓦片的横向间隔; （3）基于所述金属间隔和所述横向间隔，在匹配的装置周围放置瓦片; （4）在匹配装置周围的区域中进行密度测试; （5）如果在匹配装置周围的区域中不满足密度测试，则将匹配的装置分成至少两个子装置，并且相对于每个子装置重复计算金属间距，计算横向间隔的步骤， 并在每个子设备上放置瓷砖。 该方法还适用于多种匹配器件，包括聚电阻器，扩散电阻器，双重多晶硅电容器，金属 - 绝缘体 - 金属电容器和条纹电容器。

公开(公告)号：US07595666B2

公开(公告)日：2009-09-29

申请号：US12244214

申请日：2008-10-02

申请人： Brandt Braswell ,  David R. LoCascio

发明人： Brandt Braswell ,  David R. LoCascio

IPC分类号： H03K17/00

CPC分类号： G11C27/026

摘要： A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

摘要翻译： 如本文所述的双采样开关电容器架构包括具有对应于两个单独的放大器部分的两个单独输入的放大器。 放大器使用用于第一放大器部分的第一差分晶体管对，用于第二放大器部分的第二差分晶体管对，用于第一差分晶体管对的第一尾电流偏置装置，以及用于第二差分晶体管的第二尾电流偏置装置 对。 尾电流偏置装置由偏置开关结构驱动，交替地激活一个尾电流偏压装置，同时至少部分地去激活另一尾电流偏置装置。 放大器和偏置开关结构协调以消除否则将由单个放大器部分共享的公共寄生电容引起的增益误差。

公开(公告)号：US07449923B2

公开(公告)日：2008-11-11

申请号：US11206521

申请日：2005-08-17

申请人： Brandt Braswell ,  David R. LoCascio

发明人： Brandt Braswell ,  David R. LoCascio

IPC分类号： H03K17/00

CPC分类号： G11C27/026

摘要： A double sampled switched capacitor architecture as described herein includes an amplifier having two separate inputs corresponding to two separate amplifier sections. The amplifier uses a first differential transistor pair for the first amplifier section, a second differential transistor pair for the second amplifier section, a first tail current bias arrangement for the first differential transistor pair, and a second tail current bias arrangement for the second differential transistor pair. The tail current bias arrangements are driven by a bias switching architecture that alternately activates one tail current bias arrangement while at least partially deactivating the other tail current bias arrangement. The amplifier and bias switching architecture cooperate to eliminate gain error that would otherwise be caused by a common parasitic capacitance shared by a single amplifier section.

摘要翻译： 如本文所述的双采样开关电容器架构包括具有对应于两个单独的放大器部分的两个单独输入的放大器。 放大器使用用于第一放大器部分的第一差分晶体管对，用于第二放大器部分的第二差分晶体管对，用于第一差分晶体管对的第一尾电流偏置装置，以及用于第二差分晶体管的第二尾电流偏置装置 对。 尾电流偏置装置由偏置开关结构驱动，交替地激活一个尾电流偏压装置，同时至少部分地去激活另一尾电流偏置装置。 放大器和偏置开关结构协调以消除否则将由单个放大器部分共享的公共寄生电容引起的增益误差。

公开(公告)号：US07307572B2

公开(公告)日：2007-12-11

申请号：US11154416

申请日：2005-06-15

申请人： Douglas A. Garrity ,  Brandt Braswell ,  David R. Locascio

发明人： Douglas A. Garrity ,  Brandt Braswell ,  David R. Locascio

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/167 ,  H03M1/804

摘要： A switched-capacitor gain stage suitable for use with a pipelined analog to digital converter (“ADC”) is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase), and the gain stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The gain stage provides equal input loading for the input stages, which enhances the performance of the ADC.

摘要翻译： 适用于流水线模数转换器（“ADC”）的开关电容器增益级能够处理两个或多个输入通道。 来自多个通道的模拟输入电压被同时采样（每隔一个时钟相位），增益级使用双采样技术处理采样，产生残余电压采样（每个时钟相位），并为多个通道生成数字输出 交替的方式。 增益级为输入级提供相等的输入负载，增强了ADC的性能。

公开(公告)号：US07443333B2

公开(公告)日：2008-10-28

申请号：US11674435

申请日：2007-02-13

申请人： Douglas A. Garrity ,  David R. Locascio

发明人： Douglas A. Garrity ,  David R. Locascio

IPC分类号： H03M1/34

CPC分类号： H03M1/46

摘要： A converter (200) adapted to convert an analog input signal into a digital output signal includes an analog input terminal (205) for receiving the analog input signal, a Redundant Signed Digit (RSD) stage (210) coupled to the analog input terminal, and a digital section (220). The RSD stage is configured to receive the analog input signal at the analog input terminal, produce a first number of bits at a digital output from the analog input signal during a first half of a first clock cycle, provide a residual feedback signal of the analog input signal at the analog input terminal during a second half of the first clock cycle, and produce a second number of bits at the digital output from the residual feedback signal during a first half of a second clock cycle, the second number of bits less than the first number of bits.

摘要翻译： 适于将模拟输入信号转换为数字输出信号的A转换器（200）包括用于接收模拟输入信号的模拟输入端（205），耦合到模拟输入端的冗余有符号（RSD）级（210） 和数字部分（220）。 RSD级被配置为在模拟输入端子处接收模拟输入信号，在第一时钟周期的前半部分期间，从模拟输入信号的数字输出产生第一数量的位，提供模拟量的残留反馈信号 在第一时钟周期的后半段期间在模拟输入端子处输入信号，并且在第二时钟周期的前半部分期间从剩余反馈信号在数字输出处产生第二数量的位，第二个位数小于 第一位数。