公开(公告)号：US20120300558A1

公开(公告)日：2012-11-29

申请号：US13569856

申请日：2012-08-08

申请人： Simon J. Lovett ,  Dean Gans

发明人： Simon J. Lovett ,  Dean Gans

IPC分类号： G11C7/10 ,  G11C7/22

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104 ,  G11C2207/2254

摘要： According to one embodiment, a device for synchronizing data output from two or more memory arrays that includes a plurality of sense circuits configured to be responsive to a clock signal. The device further includes a plurality of latches and a tracking circuit. The tracking circuit may be configured to produce a control signal responsive to the clock signal. The control signal may be operable to enable the plurality of latches. The tracking has an associated delay that is substantially the same as a delay associated with at least one of the plurality of sense circuits.

摘要翻译： 根据一个实施例，一种用于同步从两个或更多个存储器阵列输出的数据的装置，其包括被配置为响应于时钟信号的多个感测电路。 该装置还包括多个锁存器和跟踪电路。 跟踪电路可以被配置为产生响应于时钟信号的控制信号。 控制信号可操作以使多个锁存器能够使能。 跟踪具有与多个感测电路中的至少一个相关联的延迟基本上相同的相关延迟。

公开(公告)号：US20070050668A1

公开(公告)日：2007-03-01

申请号：US11218193

申请日：2005-09-01

申请人： Dean Gans

发明人： Dean Gans

IPC分类号： G06F11/00

CPC分类号： G11C29/42 ,  G06F11/1048 ,  G06F11/2215 ,  G11C2029/0411

摘要： The present disclosure enables individual bits of a data signal to be flipped (their state changed from logic one to logic zero or vice versa) to mimic an error. By flipping various bits or combinations of bits, various predetermined errors can be forced. By measuring the time delay between when uncorrected data is output from the memory device and when corrected data is output, the time the error correction circuitry takes to correct each of the forced errors can be measured and the part characterized according to the various measurements. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 本公开使得可以翻转数据信号的各个位（它们的状态从逻辑1变为逻辑0，反之亦然），以模拟错误。 通过翻转各种位或位的组合，可以强制各种预定的错误。 通过测量从存储器件输出未校正的数据和输出校正数据之间的时间延迟，可以测量误差校正电路用于校正每个强制误差的时间，并且可以根据各种测量来表征该部分。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US20050002250A1

公开(公告)日：2005-01-06

申请号：US10901644

申请日：2004-07-28

申请人： Dean Gans

发明人： Dean Gans

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  H03F3/45 ,  H03K5/24

CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C2207/005 ,  H03K5/2481 ,  H03K5/249

摘要： A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.

公开(公告)号：US6161204A

公开(公告)日：2000-12-12

申请号：US24826

申请日：1998-02-17

申请人： Dean Gans

发明人： Dean Gans

IPC分类号： G11C29/50 ,  G11C29/00

CPC分类号： G11C29/50008 ,  G11C11/41 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5004

摘要： A write driver circuit includes a drive circuit having a first drive node adapted to receive a first voltage, a second drive node, an input adapted to receive a data signal, and an output. The drive circuit couples the output to the first voltage node when the data signal has a first logic voltage, and couples the output to the second drive node when the data signal has a second logic voltage. A test circuit has an input adapted to receive a test mode signal, and an output coupled to the second drive node. The test circuit develops a first impedance between the second drive node and a second voltage source when the test mode signal is active, and develops a second impedance between the second drive node and the second voltage source when the, test mode signal is inactive.

摘要翻译： 写驱动器电路包括具有适于接收第一电压的第一驱动节点，第二驱动节点，适于接收数据信号的输入和输出的驱动电路。 当数据信号具有第一逻辑电压时，驱动电路将输出耦合到第一电压节点，并且当数据信号具有第二逻辑电压时，将输出耦合到第二驱动节点。 测试电路具有适于接收测试模式信号的输入和耦合到第二驱动节点的输出。 当测试模式信号有效时，测试电路在第二驱动节点和第二电压源之间产生第一阻抗，并且当测试模式信号无效时，在第二驱动节点和第二电压源之间产生第二阻抗。

公开(公告)号：US07660172B2

公开(公告)日：2010-02-09

申请号：US12077577

申请日：2008-03-20

申请人： Simon J. Lovett ,  Dean Gans

发明人： Simon J. Lovett ,  Dean Gans

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104 ,  G11C2207/2254

摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。 数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。 跟踪电路响应于时钟信号以产生控制信号。 多个锁存器响应于用于锁存来自总线的数据的控制信号。 控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。 该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。 可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。 例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现 放大器 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US20070189087A1

公开(公告)日：2007-08-16

申请号：US11786551

申请日：2007-04-11

申请人： Simon Lovett ,  Dean Gans

发明人： Simon Lovett ,  Dean Gans

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104 ,  G11C2207/2254

摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。 数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。 跟踪电路响应于时钟信号以产生控制信号。 多个锁存器响应于用于锁存来自总线的数据的控制信号。 控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。 该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。 可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。 例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现 放大器 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US07215585B2

公开(公告)日：2007-05-08

申请号：US11218194

申请日：2005-09-01

申请人： Simon J. Lovett ,  Dean Gans

发明人： Simon J. Lovett ,  Dean Gans

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104 ,  G11C2207/2254

摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

公开(公告)号：US20050276136A1

公开(公告)日：2005-12-15

申请号：US11210608

申请日：2005-08-23

申请人： Dean Gans

发明人： Dean Gans

IPC分类号： G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  H03F3/45 ,  H03K5/24

CPC分类号： G11C7/1069 ,  G11C7/065 ,  G11C7/08 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C2207/005 ,  H03K5/2481 ,  H03K5/249

摘要： A sense amplifier for use in a memory device and in a memory-resident system. The sense amplifier operates on a lower voltage consistent with the voltage range of the differential input data and the sense amplifier further operates on a higher voltage to level-shift the output signal concurrently with the sensing operation. The sense amplifier includes a pair of differential cross-coupled inverters whose inputs are coupled to receive the data from the memory. Once the input nodes of the cross-coupled inverters are charged, the cross-coupled inverters are further coupled to pull-up and pull-down circuits that span the higher voltage range for performing the level-shifting functionality. In order to recondition the sense amplifier for a subsequent sensing process, a clamp circuit shorts the level-shifted outputs together to prevent a higher voltage level from being inadvertently passed to the memory device when isolating pass gates are reactivated.

摘要翻译： 一种用于存储器件和存储器驻留系统中的读出放大器。 读出放大器工作在与差分输入数据的电压范围一致的较低电压下，并且读出放大器进一步在更高的电压下工作，以与感测操作同时对输出信号进行电平移位。 读出放大器包括一对差分交叉耦合的反相器，其输入被耦合以从存储器接收数据。 一旦交叉耦合的反相器的输入节点被充电，交叉耦合的反相器又被耦合到跨越更高电压范围的上拉和下拉电路，以执行电平转换功能。 为了对读出放大器进行再调整以用于随后的感测处理，钳位电路将电平移位的输出一起短路，以防止当隔离通道重新激活时，较高的电压电平被无意地传递到存储器件。

公开(公告)号：US06507924B1

公开(公告)日：2003-01-14

申请号：US09735441

申请日：2000-12-12

申请人： Dean Gans

发明人： Dean Gans

IPC分类号： G11C2900

CPC分类号： G11C29/50008 ,  G11C11/41 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5004

摘要： A write driver circuit includes a drive circuit having a first drive node adapted to receive a first voltage, a second drive node, an input adapted to receive a data signal, and an output. The drive circuit couples the output to the first voltage node when the data signal has a first logic voltage, and couples the output to the second drive node when the data signal has a second logic voltage. A test circuit has an input adapted to receive a test mode signal, and an output coupled to the second drive node. The test circuit develops a first impedance between the second drive node and a second voltage source when the test mode signal is active, and develops a second impedance between the second drive node and the second voltage source when the test mode signal is inactive.

摘要翻译： 写驱动器电路包括具有适于接收第一电压的第一驱动节点，第二驱动节点，适于接收数据信号的输入和输出的驱动电路。 当数据信号具有第一逻辑电压时，驱动电路将输出耦合到第一电压节点，并且当数据信号具有第二逻辑电压时，将输出耦合到第二驱动节点。 测试电路具有适于接收测试模式信号的输入和耦合到第二驱动节点的输出。 当测试模式信号有效时，测试电路在第二驱动节点和第二电压源之间产生第一阻抗，并且当测试模式信号无效时，在第二驱动节点和第二电压源之间产生第二阻抗。

公开(公告)号：US06388926B1

公开(公告)日：2002-05-14

申请号：US09361009

申请日：1999-07-27

申请人： Dean Gans ,  Kevin Devereaux

发明人： Dean Gans ,  Kevin Devereaux

IPC分类号： G11C2900

CPC分类号： G01R31/31701 ,  G11C5/146

摘要： An integrated circuit is described which includes a test mode circuit that allows a substrate of the integrated circuit to be forced to a voltage level dictated by an external connection during a test operation, and provides an improved substrate isolation from the external connection during non-test operations. Both n-channel transistor and p-channel transistor isolation circuit embodiments are described. An integrated circuit memory device is described which incorporated the test mode and isolation circuits. The external connection can be coupled to a negative voltage during non-test operation which is more negative than a threshold voltage below a substrate voltage without inadvertently coupling the external connection and substrate together.

摘要翻译： 描述了一种集成电路，其包括测试模式电路，其允许集成电路的基板在测试操作期间被强制为由外部连接所规定的电压电平，并且在非测试期间提供改进的与外部连接的基板隔离 操作。 描述n沟道晶体管和p沟道晶体管隔离电路实施例。 描述了集成了测试模式和隔离电路的集成电路存储器件。 外部连接可以在非测试操作期间耦合到负电压，该负电压比低于衬底电压的阈值电压更负，而不会无意中将外部连接和衬底耦合在一起。