-
公开(公告)号：US08670286B2
公开(公告)日：2014-03-11
申请号：US13431826
申请日：2012-03-27
申请人： Simon J. Lovett
发明人： Simon J. Lovett
CPC分类号： G11C8/06 , G11C8/08 , G11C11/413
摘要： Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed are determined from external memory addresses and the row decoder for the portions of the memory array to be accessed are selectively provided with electrical power. The section of memory is then accessed. One such array includes memory section voltage supply rails having decoder circuits coupled to receive electrical power, and further includes memory section power control logic. The control logic selectively couples the memory section voltage supply rail to a primary voltage supply to provide electrical power to the memory section voltage supply rail in response to being selected based on memory addresses.
摘要翻译： 公开了用于向存储器阵列的存储器部分选择性地提供电功率的存储器，存储器阵列和方法。 存储器阵列可以通过将存储器阵列未被访问而将行解码器电路解耦以接收电力来操作。 要访问的存储器阵列的部分由外部存储器地址确定，并且用于要访问的存储器阵列的部分的行解码器被选择性地提供电力。 然后访问内存部分。 一个这样的阵列包括具有耦合以接收电功率的解码器电路的存储器部分电压供应轨，并且还包括存储器部分功率控制逻辑。 响应于基于存储器地址选择，控制逻辑选择性地将存储器部分电压供应轨耦合到初级电压源以向存储器部分电压供应轨提供电力。
-
公开(公告)号：US08599629B2
公开(公告)日：2013-12-03
申请号：US13569856
申请日：2012-08-08
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a device for synchronizing data output from two or more memory arrays that includes a plurality of sense circuits configured to be responsive to a clock signal. The device further includes a plurality of latches and a tracking circuit. The tracking circuit may be configured to produce a control signal responsive to the clock signal. The control signal may be operable to enable the plurality of latches. The tracking has an associated delay that is substantially the same as a delay associated with at least one of the plurality of sense circuits.
摘要翻译： 根据一个实施例，一种用于同步从两个或更多个存储器阵列输出的数据的装置，其包括被配置为响应于时钟信号的多个感测电路。 该装置还包括多个锁存器和跟踪电路。 跟踪电路可以被配置为产生响应于时钟信号的控制信号。 控制信号可操作以使多个锁存器能够使能。 跟踪具有与多个感测电路中的至少一个相关联的延迟基本上相同的相关延迟。
-
公开(公告)号：US08248870B2
公开(公告)日：2012-08-21
申请号：US12684449
申请日：2010-01-08
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译： 根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。 数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。 跟踪电路响应于时钟信号以产生控制信号。 多个锁存器响应于用于锁存来自总线的数据的控制信号。 控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。 该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。 可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。 例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现 放大器 由于管理摘要的规则，本摘要不应用于解释索赔。
-
公开(公告)号：US20120182820A1
公开(公告)日：2012-07-19
申请号：US13431826
申请日：2012-03-27
申请人： Simon J. Lovett
发明人： Simon J. Lovett
CPC分类号： G11C8/06 , G11C8/08 , G11C11/413
摘要： Memories, memory arrays, and methods for selectively providing electrical power to memory sections of a memory array are disclosed. A memory array can be operated by decoupling row decoder circuitry from receiving electrical power while the memory array is not being accessed. Portions of the memory array to be accessed are determined from external memory addresses and the row decoder for the portions of the memory array to be accessed are selectively provided with electrical power. The section of memory is then accessed. One such array includes memory section voltage supply rails having decoder circuits coupled to receive electrical power, and further includes memory section power control logic. The control logic selectively couples the memory section voltage supply rail to a primary voltage supply to provide electrical power to the memory section voltage supply rail in response to being selected based on memory addresses.
摘要翻译： 公开了用于向存储器阵列的存储器部分选择性地提供电功率的存储器，存储器阵列和方法。 存储器阵列可以通过将存储器阵列未被访问而将行解码器电路解耦以接收电力来操作。 要访问的存储器阵列的一部分由外部存储器地址确定，并且用于要访问的存储器阵列的部分的行解码器被选择性地提供电力。 然后访问内存部分。 一个这样的阵列包括具有耦合以接收电功率的解码器电路的存储器部分电压供应轨道，并且还包括存储器部分功率控制逻辑。 响应于基于存储器地址选择，控制逻辑选择性地将存储器部分电压供应轨耦合到初级电压源以向存储器部分电压供应轨提供电力。
-
5.发明授权公开(公告)号：US08189414B2
公开(公告)日：2012-05-29
申请号：US12772681
申请日：2010-05-03
申请人： Simon J. Lovett
发明人： Simon J. Lovett
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/065
摘要： Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated.
摘要翻译： 提供了系统，装置，存储器件，读出放大器和方法，诸如包括输入节点的系统，具有耦合到输入节点的栅极的第一晶体管和耦合到输入节点的另一个栅极的第二晶体管 。 在一个或多个实施例中，第二晶体管具有比第一晶体管更大的激活电压阈值，并且第一晶体管放大存在于输入节点上的信号。 在一个这样的实施例中，在第一晶体管放大信号之后，第二晶体管在第一晶体管被去激活时保持输入节点上的放大信号。
-
6.发明申请公开(公告)号：US20120072682A1
公开(公告)日：2012-03-22
申请号：US13308333
申请日：2011-11-30
申请人： Simon J. Lovett
发明人： Simon J. Lovett
IPC分类号： G06F12/00
CPC分类号： G06F13/4234 , G06F13/1689 , G06F13/1694 , G06F13/4243 , G11C7/1045 , G11C7/1072 , G11C11/406 , G11C11/40615 , G11C11/4076 , G11C11/413
摘要： A memory access mode detection circuit and method for detecting and initiating memory access modes for a memory device The memory access mode detection circuit receives the memory address signals, the control signals, and the clock signal and generates a first mode detection signal in response to receipt of the memory address signals or a first combination of control signals. An first mode initiation signal is generated a time delay subsequent to the detection signal to initiate the first mode memory access operation. In response to receipt of a second combination of control signals and an active clock signal, the memory access mode detection circuit further generates a second mode detection signal to initiate a second mode memory access operation and to suppress generation of the first mode detection signal, thereby canceling the first mode memory access operation.
摘要翻译： 一种存储器访问模式检测电路和方法，用于检测和启动存储器件的存储器访问模式存储器访问模式检测电路接收存储器地址信号，控制信号和时钟信号，并响应于接收产生第一模式检测信号 的存储器地址信号或控制信号的第一组合。 在检测信号之后产生第一模式启动信号，以启动第一模式存储器访问操作。 响应于接收到控制信号和活动时钟信号的第二组合，存储器访问模式检测电路还产生第二模式检测信号以启动第二模式存储器访问操作并且抑制第一模式检测信号的产生，从而 取消第一模式存储器存取操作。
-
公开(公告)号：US20100118630A1
公开(公告)日：2010-05-13
申请号：US12684449
申请日：2010-01-08
申请人： Simon J. Lovett , Dean Gans
发明人： Simon J. Lovett , Dean Gans
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/1066 , G11C7/222 , G11C2207/104 , G11C2207/2254
摘要： According to one embodiment, a combination is comprised of a plurality of sense amps, each having an input for receiving a clock signal. A data bus is for receiving data from the plurality of sense amps in response to a clock signal being input to the plurality of sense amps. A tracking circuit is responsive to the clock signal for producing a control signal. A plurality of latches is responsive to the control signal for latching data from the bus. The control signal has a delay that is equal to the time needed for a last data bit to arrive at the plurality of latches. That delay may be equal to a delay associated with inputting the clock signal to a last one of the plurality of sense amps, plus a delay of the last sense amp, plus a delay of the data bus. That amount of delay may be achieved in a number of ways which combines electrical delay with delay inherently associated with the tracking circuit's location. For example, the delay of the control signal may be achieved by locating the tracking circuit proximate to the last one of the plurality of sense amps and providing the tracking circuit with an electrical delay equal to the delay of the last one of the plurality of sense amps. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译： 根据一个实施例，组合由多个感测放大器组成，每个具有用于接收时钟信号的输入。 数据总线用于响应于输入到多个感测放大器的时钟信号而从多个感测放大器接收数据。 跟踪电路响应于时钟信号以产生控制信号。 多个锁存器响应于用于锁存来自总线的数据的控制信号。 控制信号具有等于最后数据位到达多个锁存器所需的时间的延迟。 该延迟可以等于将时钟信号输入到多个感测放大器中的最后一个，延迟最后一个感测放大器加上数据总线延迟的延迟。 可以通过多种方式实现延迟量，这些方式将电延迟与与跟踪电路的位置固有相关的延迟组合。 例如，控制信号的延迟可以通过将跟踪电路定位为接近多个感测放大器中的最后一个感测放大器并且为跟踪电路提供等于多个感测中的最后一个的延迟的电延迟来实现 放大器 由于管理摘要的规则，本摘要不应用于解释索赔。
-
公开(公告)号：US07206243B2
公开(公告)日：2007-04-17
申请号：US10969184
申请日：2004-10-21
申请人： Simon J. Lovett
发明人： Simon J. Lovett
IPC分类号： G11C7/00
CPC分类号： G11C11/404 , G11C11/405 , G11C11/406 , G11C11/40603 , G11C2211/4065
摘要： A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory cell and the complementary logic state of the stored bit is rewritten to a second storage node of the memory cell. One of the acts of rewriting is achievable faster than the other and the rewriting of the true and complementary logic states is completed upon achieving the one act of rewriting that is faster than the other.
摘要翻译： 公开了一种操作动态随机存取存储器单元的方法。 存储位的真实逻辑状态被重写到存储器单元的第一存储节点，并且存储位的互补逻辑状态被重写到存储器单元的第二存储节点。 重写行为之一可以比另一个更快地实现，并且在实现比另一个更快的一次重写动作时完成对真实和互补逻辑状态的重写。
-
公开(公告)号：US06845054B2
公开(公告)日：2005-01-18
申请号：US10230046
申请日：2002-08-28
CPC分类号： G11C5/141
摘要： A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.
-
公开(公告)号：US06839297B2
公开(公告)日：2005-01-04
申请号：US10436166
申请日：2003-05-13
申请人： Simon J. Lovett
发明人： Simon J. Lovett
IPC分类号： G11C11/405 , G11C11/406 , G11C7/00
CPC分类号： G11C11/404 , G11C11/405 , G11C11/406 , G11C11/40603 , G11C2211/4065
摘要： A method of operating a dynamic random access memory cell is disclosed. The true logic state of a stored bit is rewritten to a first storage node of the memory cell and the complementary logic state of the stored bit is rewritten to a second storage node of the memory cell. One of the acts of rewriting is achievable faster than the other and the rewriting of the true and complementary logic states is completed upon achieving the one act of rewriting that is faster than the other.
-
-
-
-
-
-
-
-
-
搜索结果
63 条记录 (耗时 0.024 秒)
