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公开(公告)号：US09385739B1
公开(公告)日：2016-07-05
申请号：US14739508
申请日：2015-06-15
CPC分类号： H03M1/466
摘要： The present invention relates to a circuit for converting between an analog input voltage and a corresponding digital representation of the analog input voltage. First, second and third capacitors are used, the first and second capacitors being matched, the third capacitor serving as an accumulator. A first switch is coupled to one end of the first capacitor, and a second switch is coupled between the one end of the first capacitor and one end of the second capacitor. A third switch coupled between the one end of the second capacitor and one end of the third capacitor, with a discharge circuit being coupled between the one end of the third capacitor and an opposite end of the second capacitor. When the third switch is closed the discharge circuit fully discharges the second capacitor onto the third capacitor. The third switch is closed when the analog input voltage is greater than a reference voltage, and wherein the first switch is closed to discharge the first capacitor followed by opening the first switch and closing the second switch to cause charge on the second capacitor to divide equally between the first and second capacitors when the analog input voltage is not greater than the reference voltage. Logic circuitry may also control the conversion according to a clock pulse.
摘要翻译： 本发明涉及一种用于在模拟输入电压和相应的模拟输入电压的数字表示之间进行转换的电路。 首先，使用第二和第三电容器，第一和第二电容器匹配，第三电容器用作累加器。 第一开关耦合到第一电容器的一端，第二开关耦合在第一电容器的一端和第二电容器的一端之间。 第三开关，其耦合在第二电容器的一端和第三电容器的一端之间，放电电路耦合在第三电容器的一端和第二电容器的相对端之间。 当第三开关闭合时，放电电路将第二电容器完全放电到第三电容器上。 当模拟输入电压大于参考电压时，第三开关闭合，并且其中第一开关闭合以对第一电容器放电，随后打开第一开关并闭合第二开关以使第二电容器上的电荷平均分配 当模拟输入电压不大于参考电压时，在第一和第二电容器之间。 逻辑电路还可以根据时钟脉冲控制转换。
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公开(公告)号：US5673048A
公开(公告)日：1997-09-30
申请号：US423008
申请日：1995-04-14
CPC分类号： G11C8/10
摘要： An analog voltage address decoder circuit and stackable voltage comparator circuit are provided. The address decoder circuit has a column decode comparator network made up of a first plurality of interconnected comparator circuits and a row decode comparator network made up of a second plurality of interconnected comparator circuits. The column decode comparator network compares a plurality of reference voltages with an analog input voltage so as to detect if the analog input voltage is within a bounded window. Likewise, the row decode comparator network compares an analog input voltage with a plurality of reference voltages to detect if the analog input voltage is within a bounded window. Detection within the proper bounded windows for the rows and columns produces a corresponding "high" binary output to a particular memory location for access thereto. The decode comparator networks use stackable voltage comparator circuits to perform the voltage window comparisons. Each comparator circuit includes a differential input stage made up of a pair of transistors and receiving a current source. A current mirror is coupled to the differential input state. Successive comparator circuits are coupled together via interconnected input lines.
摘要翻译： 提供模拟电压地址解码电路和可堆叠电压比较电路。 地址解码器电路具有由第一多个互连比较器电路和由第二多个互连比较器电路组成的行解码比较器网络构成的列解码比较器网络。 列解码比较器网络将多个参考电压与模拟输入电压进行比较，以便检测模拟输入电压是否在有界窗口内。 同样，行解码比较器网络将模拟输入电压与多个参考电压进行比较，以检测模拟输入电压是否在有界窗口内。 针对行和列的正确的有界窗口内的检测产生对特定存储器位置的对应的“高”二进制输出以供访问。 解码比较器网络使用可堆叠电压比较器电路来执行电压窗口比较。 每个比较器电路包括由一对晶体管组成并接收电流源的差分输入级。 电流镜耦合到差分输入状态。 连续的比较器电路通过互连的输入线耦合在一起。
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公开(公告)号：US09059725B1
公开(公告)日：2015-06-16
申请号：US14319819
申请日：2014-06-30
IPC分类号： H03M1/12
CPC分类号： H03M1/466
摘要： The present invention relates to a circuit for converting between an analog input voltage and a corresponding digital representation of the analog input voltage. First, second and third capacitors are used, the first and second capacitors being matched, the third capacitor serving as an accumulator. A first switch is coupled to one end of the first capacitor, and a second switch is coupled between the one end of the first capacitor and one end of the second capacitor. A third switch coupled between the one end of the second capacitor and one end of the third capacitor, with a discharge circuit being coupled between the one end of the third capacitor and an opposite end of the second capacitor. When the third switch is closed the discharge circuit fully discharges the second capacitor onto the third capacitor. The third switch is closed when the analog input voltage is greater than a reference voltage, and wherein the first switch is closed to discharge the first capacitor followed by opening the first switch and closing the second switch to cause charge on the second capacitor to divide equally between the first and second capacitors when the analog input voltage is not greater than the reference voltage.
摘要翻译： 本发明涉及一种用于在模拟输入电压和相应的模拟输入电压的数字表示之间进行转换的电路。 首先，使用第二和第三电容器，第一和第二电容器匹配，第三电容器用作累加器。 第一开关耦合到第一电容器的一端，第二开关耦合在第一电容器的一端和第二电容器的一端之间。 第三开关，其耦合在第二电容器的一端和第三电容器的一端之间，放电电路耦合在第三电容器的一端和第二电容器的相对端之间。 当第三开关闭合时，放电电路将第二电容器完全放电到第三电容器上。 当模拟输入电压大于参考电压时，第三开关闭合，并且其中第一开关闭合以对第一电容器放电，随后打开第一开关并闭合第二开关以使第二电容器上的电荷平均分配 当模拟输入电压不大于参考电压时，在第一和第二电容器之间。
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4.发明授权Integrated differential voltage amplifier with programmable gain and input offset voltage 失效具有可编程增益和输入失调电压的集成差分电压放大器
公开(公告)号：US6011422A
公开(公告)日：2000-01-04
申请号：US113525
申请日：1998-07-10
CPC分类号： H03F3/45098 , G01D3/021 , G01D3/036 , G01L1/225 , G01L1/2281 , G01L9/065 , H03F3/45475 , H03F2203/45492 , H03F2203/45586
摘要： A multiplier and corresponding method are provided for amplifying a voltage difference between a first input voltage and a second input voltage, the multiplier being implemented with Bipolar Junction Transistor technology having high emitter resistance. The multiplier includes a first bipolar input transistor having high emitter resistance that receives the first input voltage and a second bipolar input transistor having high emitter resistance that receives the second input voltage. The multiplier also includes a first current source for generating a first current that flows through said first bipolar input transistor, a current mirror for producing a second current that is substantially equal to said first current and flows through said second bipolar input transistor. A range select impedance forms a first voltage loop with said first bipolar input transistor and said second bipolar input transistor and translates the voltage difference between the first input voltage and the second input voltage into a differential current. The differential current varies said second current and alters a base-to-emitter voltage of said second bipolar input transistor. A second voltage loop is provided that includes said second bipolar input transistor, the second voltage loop providing a relationship between said base-to-emitter voltage of said second bipolar input transistor and a multiplier current that represents the difference between the first input voltage and the second input voltage.
摘要翻译： 提供了乘法器和相应的方法来放大第一输入电压和第二输入电压之间的电压差，乘法器由具有高发射极电阻的双极结晶体管技术实现。 乘法器包括具有接收第一输入电压的高发射极电阻的第一双极输入晶体管和接收第二输入电压的具有高发射极电阻的第二双极性输入晶体管。 乘法器还包括用于产生流过所述第一双极输入晶体管的第一电流的第一电流源，用于产生基本上等于所述第一电流并流过所述第二双极性输入晶体管的第二电流的电流镜。 范围选择阻抗与所述第一双极输入晶体管和所述第二双极输入晶体管形成第一电压环路，并将第一输入电压和第二输入电压之间的电压差转换成差分电流。 差分电流改变所述第二电流并改变所述第二双极性输入晶体管的基极 - 发射极电压。 提供了包括所述第二双极性输入晶体管的第二电压回路，所述第二电压回路提供所述第二双极性输入晶体管的所述基极间发射极电压与代表所述第一输入电压与所述第二输入电压之间的差的乘法器电流之间的关系 第二输入电压。
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公开(公告)号：US5796298A
公开(公告)日：1998-08-18
申请号：US422153
申请日：1995-04-14
摘要： In accordance with the teachings of the present invention, a programmable integrated transducer amplifier circuit is provided which receives differential outputs from a transducer, such as a pressure or accelerometer transducer. The programmable integrated transducer amplifier circuit includes binary adjustable circuits that are programmed in response to binary coded signals. The binary adjustable circuits generate binary weighted currents that are employed to adjust the operating characteristics of the amplifier circuit. The binary coded signals are received from a programmable memory array which includes a plurality of memory cells that store binary information. Each of the memory cells are programmed when coupled to a programming signal. Additionally, the memory array has pretest capability for testing outputs of the memory cells prior to permanently programming the respective memory cells. Additionally, the integrated transducer amplifier circuit automatically compensates for variations in the operating temperature of the amplifier circuit. The method of temperature compensation is accomplished by operating the programmable integrated transducer amplifier circuit at a first temperature such that a temperature compensation voltage is "nulled" or is forced to equal zero. Thereafter, the integrated transducer amplifier circuit is operated at other temperatures such that the temperature compensation voltage is generated in a manner representing the difference between the first operating temperatures and the current operating temperature.
摘要翻译： 根据本发明的教导，提供了可编程集成换能器放大器电路，其接收来自诸如压力传感器或加速度计换能器的换能器的差分输出。 可编程集成传感器放大器电路包括响应于二进制编码信号编程的二进制可调电路。 二进制可调电路产生二进制加权电流，用于调整放大器电路的工作特性。 从包括存储二进制信息的多个存储器单元的可编程存储器阵列接收二进制编码信号。 当耦合到编程信号时，每个存储器单元被编程。 此外，存储器阵列具有用于在对各个存储单元进行永久编程之前测试存储器单元的输出的预测试能力。 此外，集成的换能器放大器电路自动补偿放大器电路的工作温度变化。 温度补偿的方法是通过在第一温度下操作可编程的积分换能器放大器电路来实现的，使得温度补偿电压被“零”或被迫等于零。 此后，集成的换能器放大器电路在其它温度下工作，使得以表示第一工作温度和当前工作温度之间的差异的方式产生温度补偿电压。
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公开(公告)号：US5966039A
公开(公告)日：1999-10-12
申请号：US988678
申请日：1997-12-11
摘要： A supply and temperature dependent linear signal generating circuit includes four transistors each having a unique current flowing therethrough and connected together to form a current multiplier. A first one of the currents is designed to be supply dependent and preferably adjustable in magnitude, a second one is designed to exhibit a specific temperature dependence, the third is designed to be both supply and temperature independent and the fourth current is defined as a ratio of the first three. The fourth current is, in one embodiment, impressed upon a network defined by a resistor divider and a voltage source to thereby define an output voltage V(T) that is both supply and temperature dependent according to the following equation:V(T)=KX*(T-TN),wherein KX is the slope of V(T) over temperature, T is the operating temperature and TN is a reference temperature at which V(T) is equal to zero. Preferably, TN is adjustable via the adjustable magnitude of the first current.
摘要翻译： 供应和温度依赖的线性信号发生电路包括四个晶体管，每个具有流过其中的独特电流并连接在一起以形成电流倍增器。 电流中的第一个被设计为取决于电源，并且优选地在数量上可调节，第二电流被设计为表现出特定的温度依赖性，第三个被设计为既供应也不依赖于温度，并且将第四电流定义为比率 的前三名。 在一个实施例中，第四电流被施加在由电阻器分压器和电压源限定的网络上，从而根据以下等式定义供应和温度依赖的输出电压V（T）：V（T）= KX *（T-TN），其中KX是V（T）相对于温度的斜率，T是工作温度，TN是V（T）等于零的参考温度。 优选地，TN可以通过第一电流的可调大小来调节。
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公开(公告)号：US5796655A
公开(公告)日：1998-08-18
申请号：US954152
申请日：1997-10-20
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A memory cell having programming voltage margin verification is provided. The memory cell includes a voltage comparator having a differential input with first and second inputs and bias circuitry for generating a differential input voltage. A voltage offset is applied to the second input of the comparator to provide an input offset voltage. A programming voltage is received for programming the memory cell and the memory cell provides an output signal. To verify an unprogrammed state voltage margin of the memory cell, a margin detection circuitry receives a verification check signal and the output is monitored to determine whether the unprogrammed state voltage margin is proper. To verify a proper programmed state voltage margin of the memory cell, current is sensed through the programming input and a determination of a proper programmed state voltage margin is determined as a function of the sensed current.
摘要翻译： 提供具有编程电压裕度验证的存储单元。 存储单元包括具有差分输入的电压比较器，其具有用于产生差分输入电压的第一和第二输入和偏置电路。 电压偏移被施加到比较器的第二输入端以提供输入偏移电压。 接收编程电压以对存储器单元进行编程，并且存储器单元提供输出信号。 为了验证存储器单元的未编程状态电压裕度，余量检测电路接收验证检查信号，并监视输出以确定未编程的状态电压裕度是否合适。 为了验证存储器单元的适当的编程状态电压裕度，通过编程输入感测电流，并且确定适当的编程状态电压余量作为感测电流的函数。
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