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    Method for correcting position-dependent distortions in patterning of integrated circuits
    1.
    发明授权
    Method for correcting position-dependent distortions in patterning of integrated circuits 有权
    用于校正集成电路图案化中的位置相关失真的方法

    公开(公告)号：US07246343B2

    公开(公告)日：2007-07-17

    申请号：US10933192

    申请日：2004-09-01

    申请人： Devendra Joshi ,  Abdurrahman Sezginer ,  Franz X. Zach

    发明人： Devendra Joshi ,  Abdurrahman Sezginer ,  Franz X. Zach

    IPC分类号： G06F17/50

    CPC分类号： G03F1/36

    摘要： A method and system for reducing the computation time required to apply position-dependent corrections to lithography, usually mask, data is disclosed. Optical proximity or process corrections are determined for a few instances of a repeating cluster or object, usually at widely separated locations and then interpolating the corrections to the other instances of the repeating cluster based on their positions in the exposure field. Or, optical proximity corrections can be applied to the repeating cluster of objects for different values of flare intensity, or another parameter of patterning imperfection, such as by calculating the value of the flare at the location of each instance of the repeating cluster, and interpolating the optical proximity corrections to those values of flare.

    摘要翻译： 公开了一种用于减少对光刻应用位置相关校正所需的计算时间的方法和系统，通常是屏蔽数据。 通常在广泛分离的位置处对重复的簇或对象的几个实例确定光学邻近度或过程校正，然后基于它们在曝光区域中的位置将校正内插到重复簇的其他实例。 或者，可以将光学邻近校正应用于不同的闪光强度值的对象的重复簇或者图案化缺陷的另一参数，例如通过计算重复簇的每个实例的位置处的闪光的值，以及内插 光学接近度校正到这些闪光值。

    Optical lithography verification process
    2.
    发明申请
    Optical lithography verification process 有权
    光刻光刻验证过程

    公开(公告)号：US20060228041A1

    公开(公告)日：2006-10-12

    申请号：US11102206

    申请日：2005-04-09

    申请人： Devendra Joshi

    发明人： Devendra Joshi

    IPC分类号： G06K9/40

    CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/705

    摘要： An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at least one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures and then detecting design phase or manufacturing phase defects in response to the filtering of the lithography simulation.

    摘要翻译： 用于光学光刻验证的装置和方法包括在具有亚光波结构的制品的至少一个设计阶段或制造阶段过滤提出的亚光波形图形的光刻模拟，然后检测响应中的设计阶段或制造阶段缺陷 对光刻模拟的滤波。

    Method for correcting position-dependent distortions in patterning of integrated circuits
    3.
    发明申请
    Method for correcting position-dependent distortions in patterning of integrated circuits 有权
    用于校正集成电路图案化中的位置相关失真的方法

    公开(公告)号：US20060048091A1

    公开(公告)日：2006-03-02

    申请号：US10933192

    申请日：2004-09-01

    申请人： Devendra Joshi ,  Abdurrahman Sezginer ,  Franz Zach

    发明人： Devendra Joshi ,  Abdurrahman Sezginer ,  Franz Zach

    IPC分类号： G06F17/50 ,  G03F1/00 ,  G21K5/00

    CPC分类号： G03F1/36

    摘要： A method and system for reducing the computation time required to apply position-dependent corrections to lithography, usually mask, data is disclosed. Optical proximity or process corrections are determined for a few instances of a repeating cluster or object, usually at widely separated locations and then interpolating the corrections to the other instances of the repeating cluster based on their positions in the exposure field. Or, optical proximity corrections can be applied to the repeating cluster of objects for different values of flare intensity, or another parameter of patterning imperfection, such as by calculating the value of the flare at the location of each instance of the repeating cluster, and interpolating the optical proximity corrections to those values of flare.

    摘要翻译： 公开了一种用于减少对光刻应用位置相关校正所需的计算时间的方法和系统，通常是屏蔽数据。 通常在广泛分离的位置处对重复的簇或对象的几个实例确定光学邻近度或过程校正，然后基于它们在曝光区域中的位置将校正内插到重复簇的其他实例。 或者，可以将光学邻近校正应用于不同的闪光强度值的对象的重复簇或者图案化缺陷的另一参数，例如通过计算重复簇的每个实例的位置处的闪光的值，以及内插 光学接近度校正到这些闪光值。

    Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design
    5.
    发明申请
    Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design 有权
    集成电路布图设计中代表性和计算复用的光罩级层次管理方法与系统

    公开(公告)号：US20060143589A1

    公开(公告)日：2006-06-29

    申请号：US11021783

    申请日：2004-12-23

    申请人： Chi-Song Horng ,  Devendra Joshi ,  Anwei Liu

    发明人： Chi-Song Horng ,  Devendra Joshi ,  Anwei Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

    摘要： A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.

    摘要翻译： 分层表示使用单元定义（CellDef）的概念来封装子电路的详细内部组成。 CellDef作为操作重用的自然单元。 如果基于CellDef或一个单元实例的分析或操作所需的计算（例如寄生提取，RET，设计规则确认（DRC）或OPC））可以无需或最小的额外努力应用于所有或重要的 单元的其他实例的子集可以实现计算量的非常大的减少。 此外，分层表示还允许将整个分析/操作任务划分成子任务的集合，例如子集。 每个CellDef一个。 然后可以将多个作业分布在网络上的大量计算节点上以用于并发执行。 虽然这可能不会减少总体计算时间，但总体周转时间（TAT）的大幅减少本身就是非常有益的。

    Defect filtering optical verification process
    6.
    发明授权
    Defect filtering optical verification process 有权
    缺陷过滤光学验证过程

    公开(公告)号：US08161423B1

    公开(公告)日：2012-04-17

    申请号：US12407718

    申请日：2009-03-19

    申请人： Devendra Joshi

    发明人： Devendra Joshi

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/705

    摘要： An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at feast one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures and then detecting design phase or manufacturing phase defects in response to the filtering of the lithography simulation.

    摘要翻译： 用于光学光刻验证的装置和方法包括：在具有亚光波结构的制造物品的一个设计阶段或制造阶段期间过滤所提出的亚光波形图形的光刻模拟，然后检测响应中的设计阶段或制造阶段缺陷 对光刻模拟的滤波。

    Defect filtering optical lithography verification process
    9.
    发明授权
    Defect filtering optical lithography verification process 有权
    缺陷过滤光刻光刻验证过程

    公开(公告)号：US07530048B2

    公开(公告)日：2009-05-05

    申请号：US11102206

    申请日：2005-04-09

    申请人： Devendra Joshi

    发明人： Devendra Joshi

    IPC分类号： G06F17/50

    CPC分类号： G03F7/70441 ,  G03F1/36 ,  G03F7/705

    摘要： An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at least one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures and then detecting design phase or manufacturing phase defects in response to the filtering of the lithography simulation.

    摘要翻译： 用于光学光刻验证的装置和方法包括在具有亚光波结构的制品的至少一个设计阶段或制造阶段过滤提出的亚光波形图形的光刻模拟，然后检测响应中的设计阶段或制造阶段缺陷 对光刻模拟的滤波。

    Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design
    10.
    发明授权
    Method and system for reticle-wide hierarchy management for representational and computational reuse in integrated circuit layout design 有权
    集成电路布图设计中代表性和计算复用的光罩级层次管理方法与系统

    公开(公告)号：US07401319B2

    公开(公告)日：2008-07-15

    申请号：US11021783

    申请日：2004-12-23

    申请人： Chi-Song Horng ,  Devendra Joshi ,  Anwei Liu

    发明人： Chi-Song Horng ,  Devendra Joshi ,  Anwei Liu

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G03F1/00 ,  G21K5/00

    CPC分类号： G06F17/5072 ,  G06F2217/12 ,  Y02P90/265

    摘要： A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.

    摘要翻译： 分层表示使用单元定义（CellDef）的概念来封装子电路的详细内部组成。 CellDef作为操作重用的自然单元。 如果基于CellDef或一个单元实例的分析或操作所需的计算（例如寄生提取，RET，设计规则确认（DRC）或OPC））可以无需或最小的额外努力应用于所有或重要的 单元的其他实例的子集可以实现计算量的非常大的减少。 此外，分层表示还允许将整个分析/操作任务划分成子任务的集合，例如子集。 每个CellDef一个。 然后可以将多个作业分布在网络上的大量计算节点上以用于并发执行。 虽然这可能不会减少总体计算时间，但总体周转时间（TAT）的大幅减少本身就是非常有益的。